Intel 5-level paging: Difference between revisions

Revision as of 23:37, 11 March 2020

Revision as of 23:48, 11 March 2020

Line 6:

Current [[x86-64]] processors use a four-level page table structure when operating in 64-bit mode.<ref name="x86-software-developers-manual" />{{Rp|2806}} A similar situation arose when the 32 bit [[IA-32]] processors used two levels, allowing up to four [[GiB]] of memory (both virtual and physical). To support more than 4&nbsp;GB of [[RAM]], an additional mode of address translation called [[Physical Address Extension]] (PAE) was defined, involving a third level.<ref>{{Cite web|url=https://docs.microsoft.com/en-us/previous-versions/windows/hardware/design/dn613969(v=vs.85)|title=Operating Systems and PAE Support - Windows 10 hardware dev|last=Hudek|first=Ted|website=docs.microsoft.com|language=en-us|access-date=2018-04-26}}</ref> This was enabled by setting a bit in [[Control register#CR4|the CR4 register]].<ref name="x86-software-developers-manual" />{{Rp|2799}} Likewise, the new extension is enabled by setting bit 12 of the CR4 register (known as LA57).<ref name="intel-white-paper" />{{Rp|16}} This is only used when the processor is operating in 64 bit mode, and only may be modified when it is not.<ref name="intel-white-paper" />{{Rp|16}} If the bit is not set, the processor operates with four paging levels.

The new extensions allow up to 4&nbsp;PiB of physical memory,<ref name="phoronix" /> compared to the maximum of 256&nbsp;TB on previous processors.<ref name="amd10h">{{cite web|url=http://developer.amd.com/wordpress/media/2012/10/31116.pdf|title=BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h Processors|page=24|accessdate=2018-04-26|quote=Physical address space increased to 48 bits.}}</ref> As adding another page table multiplies the address space by 512, the virtual limit has increased from 256&nbsp;TiB to 128&nbsp;PiB. An extra nine bits of the virtual address index the new table, so while formerly bits&nbsp;0 through&nbsp;47 were in use, now bits&nbsp;0 through&nbsp;56 are in use.

As with four level paging, the high-order bits of a virtual address that do not participate in address translation must be the same as the most significant implemented bit. With five-level paging enabled, this means that bits&nbsp;57 through&nbsp;63 must be copies of bit&nbsp;56.<ref name="intel-white-paper" />{{Rp|17}} Intel has renamed the existing paging system as "4-level paging", which used to be known as [[IA-32e]] paging.<ref name="x86-software-developers-manual" />{{Rp|2788}}