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This is an example of [[SystemVerilog]] code which finds the maximum value in the array in only 2 clock cycles. It compares all the combinations of the elements in the array at the first clock, and merges the result at the second clock. It uses CRCW memory; <code>m[i] <= 1</code> and <code>maxNo <= data[i]</code> are written concurrently. The concurrency causes no conflicts because the algorithm guarantees that the same value is written to the same memory. This code can be run on [[Field-programmable gate array|FPGA]] hardware.
<
module FindMax #(parameter int len = 8)
(input bit clock, resetN, input bit[7:0] data[len], output bit[7:0] maxNo);
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end
endmodule
</syntaxhighlight>
== See also ==
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