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Giraffedata (talk | contribs) clarify |
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The ''xAPIC'' was introduced with the [[Pentium 4]], while the ''x2APIC'' is the most recent generation of the Intel's programmable interrupt controller, introduced with the [[Nehalem (microarchitecture)|Nehalem microarchitecture]] in November 2008.<ref>{{cite web|url=http://www.computerbase.de/bildstrecke/20069/27/|title=Intel Nehalem mit X2APIC - Extended xAPIC Architecture (Bild 27/27) - ComputerBase|website=www.computerbase.de}}</ref> The major improvements of the x2APIC address the number of supported CPUs and performance of the interface.
The x2APIC now uses 32 bits to address CPUs, allowing to address up to 2<sup>32</sup> − 1 CPUs using the physical destination mode. The logical destination mode now works differently and introduces clusters; using this mode, one can address up to 2<sup>20</sup> − 16 processors
The improved interface reduces the number of needed APIC register access for sending [[Inter-processor interrupt]]s (IPIs). Because of this advantage, [[Kernel-based Virtual Machine|KVM]] can and does emulate the x2APIC for older processors that do not physically support it, and this support is exposed from [[QEMU]] going back to [[Conroe (microprocessor)|Conroe]] and even for AMD [[Opteron]] G-series processors (neither of which natively support x2APIC).<ref>{{cite web|url=https://lists.gnu.org/archive/html/qemu-devel/2013-07/msg03756.html|title=Re: [Qemu-devel] [Question] why x2apic's set by default without host sup|website=lists.gnu.org}}</ref><ref>{{cite web|url=http://lists.nongnu.org/archive/html/qemu-devel/2014-01/msg02441.html|title=[Qemu-devel] [PATCH] target-i386: enable x2apic by default on more recen|website=lists.nongnu.org}}</ref>
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