The PPU is an Inin-Orderorder processor, but it has some unique traits which allow it to achieve some benefits of Outout-of-Orderorder execution without expensive re-ordering hardware. Upon reaching an L1 cache miss - it can execute past the cache miss, stopping only when an instruction is actually dependent on a load. It can send up to 8 load instructions to the L2 cache out-of-order. It has an instruction delay pipe - a side path that allows it to execute instructions that would normally cause [[Bubble (computing)|pipeline stalls]] without holding up the rest of the [[Instruction pipeline|pipeline]]. The instruction delay pipeline is used for the Out-Of-Order Load/Stores: cache misses are put there while it moves on.
