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In the [[history of computing hardware|history of computer hardware]], some early [[reduced instruction set computer]] [[central processing unit]]s (RISC CPUs) used a very similar architectural solution, now called a '''classic RISC pipeline'''. Those CPUs were: [[MIPS architecture|MIPS]], [[SPARC]], Motorola [[Motorola 88000|88000]], and later the notional CPU [[DLX]] invented for education.
Each of these classic scalar RISC designs fetchedfetches and triedtries to execute [[Instructions per cycle|one instruction per cycle]]. The main common concept of each design wasis a five-stage execution [[instruction pipeline]]. During operation, each pipeline stage workedworks on one instruction at a time. Each of these stages consistedconsists of an initiala set of [[flip-flop (electronics)|flip-flops]] to hold state, and [[combinational logic]] that operatedoperates on the outputs of those flip-flops.
==The classic five stage RISC pipeline==
===Instruction fetch===
The instructions reside in memory that takes one cycle to read. This memory can be dedicated SRAM, or an Instruction [[Cache (computing)|Cache]]. on theseThe machinesterm had"latency" ais latencyused ofin onecomputer cyclescience often, meaningand that ifmeans the instructiontime wasfrom inwhen thean cache,operation starts until it wouldcompletes. be readyThus, oninstruction thefetch nexthas a latency of one [[clock cycle]] (if using single cycle SRAM or if the instruction was in the cache). During Thus, during the [[Instruction fetch|Instruction Fetch]] stage, a 32-bit instruction wasis fetched from the cacheinstruction memory.
The [[Program Counter]], or PC, is a register that holds the address ofthat theis currentpresented to the instruction memory. ItAt feedsthe intostart theof PCa predictorcycle, whichthe thenaddress sendsis thepresented [[Programto Counter]]instruction (PC)memory. to Then during the Instructioncycle, Cachethe toinstruction is being read theout currentof instruction. memory, Atand at the same time, thea PCcalculation predictoris predictsdone to determine the addressnext PC. The calculation of the next instructionPC is done by incrementing the PC by 4, and by choosing whether to take that as the next PC or alternatively to take the result of a branch / jump calculation as the next PC. Note that in classic RISC, (all instructions werehave 4the bytessame long)length. (This predictionis wasone thing that separates RISC from CISC <ref>{{cite paper |first=David |last=Patterson| title=RISC I: A Reduced Instruction Set VLSI Computer |url=https://dl.acm.org/doi/10.5555/800052.801895}}</ref>). In the original RISC designs, the size of an instruction is 4 bytes, so always wrongadd 4 to the instruction address, but don't use PC + 4 for in the case of a taken branch, jump, or exception (see '''delayed branches''', below). Later(Note machinesthat wouldsome modern machines use more complicated and accurate algorithms ([[branch prediction]] and [[branch target predictor|branch target prediction]]) to guess the next instruction address.)
===Instruction decode===
UnlikeAnother thing that separates the first RISC machines from earlier microcodedCISC machines, theis firstthat RISCmachinesRISC hadhas no [[microcode]] <ref>{{cite paper |first=David |last=Patterson| title=RISC I: A Reduced Instruction Set VLSI Computer |url=https://dl.acm.org/doi/10.5555/800052.801895}}</ref>. OnceIn the case of CISC micro-coded instructions, once fetched from the instruction cache, the instruction bits wereare shifted down the pipeline, so thatwhere simple combinational logic in each pipeline stage could produce theproduces control signals for the datapath directly from the instruction bits. AsIn athose resultCISC designs, very little decoding is done in the stage traditionally called the decode stage. A consequence of this lack of decoding meant howeveris that more instruction bits hadhave to be used to specifying what the instruction shoulddoes. do (and also, what it should not), and thatThat leaves fewer bits for things like register indices.
All MIPS, SPARC, and DLX instructions have at most two register inputs. During the decode stage, the indexes of these two register namesregisters are identified within the instruction, and the indexes are presented to the register memory, as the address. Thus the two registers named are read from the [[register file]]. In the MIPS design, the register file had 32 entries.
At the same time the register file wasis read, instruction issue logic in this stage determineddetermines if the pipeline wasis ready to execute the instruction in this stage. If not, the issue logic would causecauses both the Instruction Fetch stage and the Decode stage to stall. On a stall cycle, the stagesinput wouldflip preventflops theirdo initialnot flip-flopsaccept fromnew acceptingbits, thus no new bitscalculations take place during that cycle.
If the instruction decoded wasis a branch or jump, the target address of the branch or jump wasis computed in parallel with reading the register file. The branch condition is computed in the following cycle (after the register file is read), and if the branch is taken or if the instruction is a jump, the PC predictor in the first stage is assigned the branch target, rather than the incremented PC that has been computed. Some architectures made use of the [[Arithmetic logic unit|ALU]] in the Execute stage, at the cost of slightly decreased instruction throughput.
The decode stage ended up with quite a lot of hardware: MIPS hadhas the possibility of branching if two registers wereare equal, so a 32-bit-wide AND tree ranruns in series after the register file read, making a very long critical path through this stage (which means fewer cycles per second). Also, the branch target computation generally required a 16 bit add and a 14 bit incrementer. Resolving the branch in the decode stage made it possible to have just a single-cycle branch mispredictmis-predict penalty. Since branches were very often taken (and thus mispredictedmis-predicted), it was very important to keep this penalty low.
===Execute===
During this stage, both single cycle and two cycle instructions write their results into the register file.
Note that two different stages are accessing the register file at the same time -- the decode stage is reading two source registers, at the same time that the writeback stage is writing a previous instruction's destination register.
On real silicon, this can be a hazard (see below for more on hazards). That is because one of the source registers being read in decode might be the same as the destination register being written in writeback. When that happens, then the same memory cells in the register file are being both read and written the same time. On silicon, many implementations of memory cells will not operate correctly when read and written at the same time.
==Hazards==
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