Programmable interrupt controller: Difference between revisions

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In [[computing]], a '''programmable interrupt controller''' ('''PIC''') is a device that ishelps used[[microprocessor]] to(or combine[[CPU]]) severalto sources ofhandle [[Interrupt request (PC architecture)|interrupt requests]] onto(IRQ) onecoming orfrom moremultiple [[CPU]]different lines,sources while(like allowingexternal priorityI/O levelsdevices) towhich bemay assignedcome to(get itsfired) interrupt outputssimultaneously.<ref>{{Cite Whenweb|title=Interrupt theController device- hasan multipleoverview {{!}} ScienceDirect Topics|url=https://www.sciencedirect.com/topics/engineering/interrupt-controller|access-date=2020-07-26|website=www.sciencedirect.com}}</ref> outputsIt helps to assert,prioritize itIRQs assertsso themthat inCPU switches to the ordermost ofappropriate their[[interrupt handler]] (ISR) after PIC assertes IRQ's relative priority. Common modes of a PIC include hard priorities, rotating priorities, and cascading priorities.{{Citation needed|date=July 2011}} PICs often allow the cascading of their outputs to inputs between each other. On [[PC architecture]] PIC are typically ebedded into a [[Southbridge (computing)|southbridge chips]] whose internal architecture is defined by chipsets' vendors' standards.
 
==Common features==
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==See also==
* [[Intel 8259]] - Notable PIC from Intel
* [[Advanced Programmable Interrupt Controller]] (APIC)
* [[OpenPIC and IBM MPIC]]
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* [[Interrupt latency]]
* [[Non-maskable interrupt]] (NMI)
* [[IRQL (Windows)]]
 
==Further reading==