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Changed from past tense "was" to definite "is" to remove unnecessary confusion. These 5 stage pipelines still exist. Mentally difficult to parse the "was" form. Added important details about hazards to demystify them. Removed incorrect "PC predictor" |
m →Exceptions: Add link to the translation lookaside buffer article section about TLB misses |
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But the programmer, especially if programming in a language supporting [[large numbers|large integers]] (e.g. [[Lisp (programming language)|Lisp]] or [[Scheme (programming language)|Scheme]]), may not want wrapping arithmetic. Some architectures (e.g. MIPS), define special addition operations that branch to special locations on overflow, rather than wrapping the result. Software at the target ___location is responsible for fixing the problem. This special branch is called an exception. Exceptions differ from regular branches in that the target address is not specified by the instruction itself, and the branch decision is dependent on the outcome of the instruction.
The most common kind of software-visible exception on one of the classic RISC machines is a [[Translation_lookaside_buffer#TLB-miss_handling|''TLB miss''
Exceptions are different from branches and jumps, because those other control flow changes are resolved in the decode stage. Exceptions are resolved in the writeback stage. When an exception is detected, the following instructions (earlier in the pipeline) are marked as invalid, and as they flow to the end of the pipe their results are discarded. The program counter is set to the address of a special exception handler, and special registers are written with the exception ___location and cause.
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