Intel 5-level paging: Difference between revisions

Revision as of 10:10, 18 May 2020

Revision as of 10:20, 18 May 2020

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As with four level paging, the high-order bits of a virtual address that do not participate in address translation must be the same as the most significant implemented bit. With five-level paging enabled, this means that bits&nbsp;57 through&nbsp;63 must be copies of bit&nbsp;56.<ref name="intel-white-paper" />{{Rp|17}} Intel has renamed the existing paging system as "4-level paging", which used to be known as [[IA-32e]] paging.<ref name="x86-software-developers-manual" />{{Rp|2788}}

Extending page table entry to 128 bits allows full 64-bit address space in 4-level paging scheme, and makes possible arbitrary allocation unit sizes in 5-level scheme.<Ref name=VA64/>

== Implementation ==