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Consider now a dynamic logic implementation:
[[Image:
The dynamic logic circuit requires two phases. The first phase, when ''Clock'' is low, is called the ''setup phase'' and the second phase, when ''Clock'' is high, is called the ''evaluation phase''. In the setup phase, the output is driven high unconditionally (no matter the values of the inputs ''A'' and ''B''). The [[capacitor]], which represents the load capacitance of this gate, becomes charged. Because the transistor at the bottom is turned off, it is impossible for the output to be driven low during this phase.
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A popular implementation is [[domino logic]].
==External links==
* [http://www.cmosvlsi.com/lect9.pdf Introduction to CMOS VLSI Design – Lecture 9: Circuit Families] – David Harris' lecture notes on the subject.
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