Revision as of 01:26, 14 June 2020 edit 12.30.213.227 (talk) →XS3: corrected publisher on a reference ← Previous edit		Revision as of 01:28, 14 June 2020 edit undo 12.30.213.227 (talk) →XS3: removed unnecessary link to DRAM article, as link to LPDDR is mentioned just before Next edit →
Line 58: The XS3 architecture was introduced in 2020. It is implemented by a new series of [[xcore.ai]] processors aimed at embedded and IoT devices utilizing [[Artificial_intelligence\|AI]] acceleration in [[System_on_a_chip\|SoC]]-like designs. XS3 extends the XS2 architecture with additional [[Digital_signal_processing\|DSP]] performance, new 32-bit [[Floating-point_arithmetic\|floating-point]] capability, and 256-bit-wide [[Vector_processor\|vector]] instructions. Processors based on this architecture also support a two-lane [[MIPI_Alliance\|MIPI]] interface for cameras or other sensor input, as well as a 16-bit-wide [[LPDDR]] interface for external ~~[[Dynamic_random-access_memory\|DRAM]]~~memory. Core clock speed has been increased to 800 MHz, and up to four xCONNECT links are available, providing scalability through the connection of additional xCORE processors.<ref>{{cite web \|title=XMOS announces world’s lowest cost, most flexible AI processor \|url=https://www.xmos.com/xmos-announces-worlds-lowest-cost-most-flexible-ai-processor

XCore Architecture: Difference between revisions