Classic RISC pipeline: Difference between revisions

Revision as of 08:33, 14 September 2020

Revision as of 11:36, 13 October 2020

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===Instruction decode===

Another thing that separates the first RISC machines from earlier CISC machines, is that RISC has no [[microcode]] .<ref>{{cite document |first=David |last=Patterson| title=RISC I: A Reduced Instruction Set VLSI Computer |url=https://dl.acm.org/doi/10.5555/800052.801895}}</ref>. In the case of CISC micro-coded instructions, once fetched from the instruction cache, the instruction bits are shifted down the pipeline, where simple combinational logic in each pipeline stage produces control signals for the datapath directly from the instruction bits. In those CISC designs, very little decoding is done in the stage traditionally called the decode stage. A consequence of this lack of decoding is that more instruction bits have to be used to specifying what the instruction does. That leaves fewer bits for things like register indices.

All MIPS, SPARC, and DLX instructions have at most two register inputs. During the decode stage, the indexes of these two registers are identified within the instruction, and the indexes are presented to the register memory, as the address. Thus the two registers named are read from the [[register file]]. In the MIPS design, the register file had 32 entries.