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Intel's own depletion-load NMOS process was known as '''HMOS''', for ''High density, short channel MOS''. The first version was introduced in late 1976 and first used for their [[static RAM]] products,<ref>''See http://lark.tu-sofia.bg/ntt/eusku/readings/art_1.pdf''</ref> it was soon being used for faster and/or less power hungry versions of the 8085, 8086, and other chips.
HMOS continued to be improved and went through four distinct generations. According to Intel, HMOS II (1979) provided twice the density and four times the speed/power product over other typical contemporary depletion-load nMOS processes.<ref>See for instance: ''Leo J.Scanlon The 68000 Principles and programming.''</ref> This version was widely licensed by 3rd parties, including (among others) [[Motorola]] who used it for their [[Motorola 68000]], and [[Commodore Semiconductor Group]], who used it for their [[
The original HMOS process, later referred to as HMOS I, had a channel length of 3 microns, which was reduced to 2 for the HMOS II, and 1.5 for HMOS III. By the time HMOS III was introduced in 1982, Intel had begun a switch to their [[CHMOS]] process, a [[CMOS]] process using design elements of the HMOS lines. One final version of the system was released, HMOS-IV. A significant advantage to the HMOS line was that each generation was deliberately designed to allow existing layouts to die-shrink with no major changes. Various techniques were introduced to ensure the systems worked as the layout changed.<ref>{{cite conference |conference=ISSCC 82 |date=1982 |title=HMOS III Technology}}</ref><ref>{{cite journal |journal=IEEE Journal of Solid-State Circuits |title=HMOS III Technology |date=October 1982}}</ref>
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