Depletion-load NMOS logic: Difference between revisions

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The first depletion-load nMOS circuits were pioneered and made by the [[DRAM]] manufacturer [[Mostek]], which made depletion-mode transistors available for the design of the original [[Zilog Z80]] in 1975–76.<ref>''Zilog relied on [[Mostek]] and [[Synertek]] to produce the Z80 and other chips before their own production facilities were ready.''</ref> Mostek had the [[ion implantation]] equipment needed to create a [[doping (semiconductor)|doping profile]] more precise than possible with [[diffusion]] methods, so that the [[threshold voltage]] of the load transistors could be adjusted reliably. At Intel, depletion load was introduced in 1974 by Federico Faggin, an ex-Fairchild engineer and later the founder of [[Zilog]]. Depletion-load was first employed for a redesign of one of Intel's most important products at the time, a +5V-only 1Kbit nMOS [[Static random-access memory|SRAM]] called the ''2102'' (using more than 6000 transistors<ref>''Each bit demands six transistors in a typical [[static RAM]].''</ref>). The result of this redesign was the significantly faster ''2102A'', where the highest performing versions of the chip had access times of less than 100ns, taking MOS memories close to the speed of bipolar RAMs for the first time.<ref>''See for instance: http://www.intel4004.com/sgate.htm or http://archive.computerhistory.org/resources/text/Oral_History/Faggin_Federico/Faggin_Federico_1_2_3.oral_history.2004.102658025.pdf'' {{Webarchive|url=https://web.archive.org/web/20170110232713/http://archive.computerhistory.org/resources/text/Oral_History/Faggin_Federico/Faggin_Federico_1_2_3.oral_history.2004.102658025.pdf |date=2017-01-10 }}</ref>

Depletion-load nMOS processes were also used by several other manufacturers to produce many [[incarnation]]sincarnations of popular 8-bit, 16-bit, and 32-bit CPUs. Similarly to early pMOS and nMOS CPU designs using [[Field-effect transistor#FET operation|enhancement mode]] MOSFETs as loads, depletion-load nMOS designs typically employed various types of [[dynamic logic (digital logic)|dynamic logic]] (rather than just static gates) or [[Pass transistor logic|pass transistor]]s used as dynamic [[latch (electronics)|clocked latch]]es. These techniques can enhance the area-economy considerably although the effect on the speed is complex. Processors built with depletion-load nMOS circuitry include the [[Motorola 6800|6800]] (in later versions<ref name = "M6800 redesign">{{Cite journal| title = Motorola Redesigns 6800 | journal = Microcomputer Digest | volume = 3 | issue = 2 | page =4 | publisher = Microcomputer Associates | ___location = Santa Clara, CA | date = August 1976 | url = http://www.bitsavers.org/pdf/microcomputerAssociates/Microcomputer_Digest_v03n02_Aug76.pdf}} "Motorola is redesigning the M6800 microprocessor family by adding depletion loads to increase speed and reduce the 6800 CPU size to 160 mils."</ref>), the [[6502]], [[Signetics 2650]], [[8085]], [[6809]], [[8086]], [[Z8000]], [[NS32016]], and many others (whether or not the HMOS processors below are included, as special cases).

A large number of support and peripheral ICs were also implemented using (often static) depletion-load based circuitry. However,