Single-electron transistor: Difference between revisions

Revision as of 04:57, 26 November 2020

Revision as of 08:04, 15 January 2021

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The increasing relevance of the [[Internet of things]] and the healthcare applications give more relevant impact to the electronic device power consumption. For this purpose, ultra-low-power consumption is one of the main research topics into the current electronics world. The amazing number of tiny computers used in the day-to-day world, e.g. mobile phones and home electronics; requires a significant power consumption level of the implemented devices. In this scenario, the SET has appeared as a suitable candidate to achieve this low power range with high level of device integration.

Applicable areas are among others: super-sensitive electrometers, single-electron spectroscopy, DC current standards, temperature standards, detection of infrared radiation, voltage state logics, charge state logics, programmable single-electron transistor logic.<ref>{{cite journal|last1=Kumar|first1=O.|last2=Kaur|first2=M.|title=Single Electron Transistor: Applications & Problems|journal=International Journal of VLSI Design & Communication Systems|year=2010|volume=1|issue=4|pages=24–29|doi=10.5121/vlsic.2010.1403|doi-access=free}}</ref>

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=== Principle ===

[[File:Set schematic.svg|thumb|right|Schematic diagram of a single-electron transistor.]]

[[File:Single electron transistor.svg|thumb|right|Left to right: energy levels of source, island and drain in a single-electron transistor for the blocking state (upper part) and transmitting state (lower part).]]

The SET has, like the [[field-effect transistor|FET]], three electrodes: source, drain, and a gate. The main technological difference between the transistor types is in the channel concept. While the channel changes from insulated to conductive with applied gate voltage in the FET, the SET is always insulated. The source and drain are coupled through two [[Quantum tunnelling|tunnel junctions]], separated by a metallic or semiconductor-based [[quantum dot|quantum nanodot]] (QD),<ref name="UchidaMatsuzawa2000">{{cite journal|last1=Uchida|first1=Ken|last2=Matsuzawa|first2=Kazuya|last3=Koga|first3=Junji|last4=Ohba|first4=Ryuji|last5=Takagi|first5=Shin-ichi|last6=Toriumi|first6=Akira|title=Analytical Single-Electron Transistor (SET) Model for Design and Analysis of Realistic SET Circuits|journal=Japanese Journal of Applied Physics|volume=39|issue=Part 1, No. 4B|year=2000|pages=2321–2324|issn=0021-4922|doi=10.1143/JJAP.39.2321|bibcode=2000JaJAP..39.2321U}}</ref>, also known as the "island". The electrical potential of the QD can be tuned with the capacitively coupled gate electrode to alter the resistance, by applying a positive voltage the QD will change from blocking to non-blocking state and electrons will start tunnelling to the QD. This phenomenon is known as the [[Coulomb blockade]].

The current, <math>I,</math> from source to drain follows [[Ohm's law]] when <math>V_{\rm SD}</math> is applied, and it equals <math>\tfrac{V_{\rm SD}}{R},</math> where the main contribution of the resistance, <math>R,</math> comes from the tunnelling effects when electrons move from source to QD, and from QD to drain. <math>V_{\rm G}</math> regulates the resistance of the QD, which regulates the current. This is the exact same behaviour as in regular FETs. However, when moving away from the macroscopic scale, the quantum effects will affect the current, <math>I.</math>

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The existence of the Coulomb blockade is clearly visible in the [[current–voltage characteristic]] of a SET (a graph showing how the drain current depends on the gate voltage). At low gate voltages (in absolute value), the drain current will be zero, and when the voltage increases above the threshold, the transitions behave like an ohmic resistance (both transitions have the same permeability) and the current increases linearly. The background charge in a dielectric can not only reduce, but completely block the Coulomb blockade. <math>q_0 = \pm (0.5 + m) e.</math>

In the case where the permeability of the tunnel barriers is very different <math>(R_{T1} \gg R_{T2} = R_T),</math> a stepwise I-V characteristic of the SET arises. An electron tunnels to the island through the first transition and is retained on it, due to the high tunnel resistance of the second transition. After a certain period of time, the electron tunnels through the second transition, however, this process causes a second electron to tunnel to the island through the first transition. Therefore, most of the time the island is charged in excess of one charge. For the case with the inverse dependence of permeability <math>(R_{T1} \ll R_{T2} = R_T),</math> the island will be unpopulated and its charge will decrease stepwise.{{cncitation needed|date=January 2020}} Only now can we understand the principle of operation of a SET. Its equivalent circuit can be represented as two tunnel junctions connected in series via the QD, perpendicular to the tunnel junctions is another control electrode (gate) connected. The gate electrode is connected to the island through a control tank <math>C_{\rm G}.</math> The gate electrode can change the background charge in the dielectric, since the gate additionally polarizes the island so that the island charge becomes equal to

<math>q = -ne + q_0 + C_{\rm G}(V_{\rm G} - V_{2}).</math>

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As mentioned in bullet 2 in the list above: the electrostatic charging energy must be greater than <math>k_{\rm B} T</math> to prevent thermal fluctuations affecting the [[Coulomb blockade]]. This in turn implies that the maximum allowed island capacitance is inversely proportional to the temperature, and needs to be below 1 aF to make the device operational at room temperature.

The island capacitance is a function of the QD size, and a QD diameter smaller than 10 &nbsp;nm is preferable when aiming for operation at room temperature. This in turn puts huge restraints on the manufacturability of integrated circuits because of reproducibility issues.

=== CMOS compatibility ===

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The level of the electrical current of the SET can be amplified enough to work with available [[CMOS]] technology by generating a hybrid SET-[[field-effect transistor|FET]] device.<ref name="IonescuMahapatra2004">{{cite journal|last1=Ionescu|first1=A.M.|last2=Mahapatra|first2=S.|last3=Pott|first3=V.|title=Hybrid SETMOS Architecture With Coulomb Blockade Oscillations and High Current Drive|journal=IEEE Electron Device Letters|volume=25|issue=6|year=2004|pages=411–413|issn=0741-3106|doi=10.1109/LED.2004.828558|bibcode=2004IEDL...25..411I}}</ref><ref name="AmatBausells2017">{{cite journal|last1=Amat|first1=Esteve|last2=Bausells|first2=Joan|last3=Perez-Murano|first3=Francesc|title=Exploring the Influence of Variability on Single-Electron Transistors Into SET-Based Circuits|journal=IEEE Transactions on Electron Devices|volume=64|issue=12|year=2017|pages=5172–5180|issn=0018-9383|doi=10.1109/TED.2017.2765003|bibcode=2017ITED...64.5172A}}</ref>

The EU funded, in 2016, project IONS4SET (#688072)<ref>{{cite web|url=http://www.ions4set.eu|title=IONS4SET Website|access-date=2019-09-17}}</ref> looks for the manufacturability of SET-FET circuits operative at room temperature. The main goal of this project is to design a SET-manufacturability process-flow for large-scale operations seeking to extend the use of the hybrid Set-CMOS architectures. To assure room temperature operation, single dots of diameters below 5 &nbsp;nm have to be fabricated and located between source and drain with tunnel distances of a few nanometers.<ref name="KlupfelBurenkov2016">{{cite book|last1=Klupfel|first1=F. J.|title=2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)|last2=Burenkov|first2=A.|last3=Lorenz|first3=J.|chapter=Simulation of silicon-dot-based single-electron memory devices|year=2016|pages=237–240|doi=10.1109/SISPAD.2016.7605191|isbn=978-1-5090-0818-6}}</ref>. Up to now there is no reliable process-flow to manufacture a hybrid SET-FET circuit operative at room temperature. In this context, this EU project explores a more feasible way to manufacture the SET-FET circuit by using pillar dimensions of approximately 10 &nbsp;nm.<ref name="Xu2019">{{cite arXiv |eprint=1906.09975v2|last1=Xu|first1=Xiaomo|title=Morphology modifcation of Si nanopillars under ion irradiation at elevated temperatures: Plastic deformation and controlled thinning to 10 nm|last2=Heinig|first2=Karl-Heinz|last3=Möller|first3=Wolfhard|last4=Engelmann|first4=Hans-Jürgen|last5=Klingner|first5=Nico|last6=Gharbi|first6=Ahmed|last7=Tiron|first7=Raluca|author8=Johannes von Borany|last9=Hlawacek|first9=Gregor|class=physics.app-ph|year=2019}}</ref>.

== See also ==