Revision as of 07:52, 1 December 2020 edit 奧田95 (talk \| contribs) Extended confirmed users 2,792 edits →Integrated FPUs Tags: Mobile edit Mobile web edit Advanced mobile edit ← Previous edit		Revision as of 17:24, 1 December 2020 edit undo Vincent Lefèvre (talk \| contribs) Extended confirmed users 5,222 edits m →Integrated FPUs: link on the first occurrence Next edit →
Line 38: In some cases, FPUs may be specialized, and divided between simpler floating-point operations (mainly addition and multiplication) and more complicated operations, like division. In some cases, only the simple operations may be implemented in hardware or [[microcode]], while the more complex operations are implemented as software. In some current architectures, the FPU functionality is combined with [[SIMD]] units to perform [[SIMD]] computation; an example of this is the augmentation of the [[x87]] instructions set with [[Streaming SIMD Extensions\|SSE]] instruction set in the [[x86-64]] architecture used in newer Intel and AMD processors. == Add-on FPUs ==

Floating-point unit: Difference between revisions