Revision as of 18:47, 17 December 2020 edit Tom.Reding (talk \| contribs) Autopatrolled, Extended confirmed users, Page movers, Template editors 4,364,437 edits m →Shared memory model: Enum 1 author/editor WL; WP:GenFixes on Tag: AWB ← Previous edit		Revision as of 00:32, 29 December 2020 edit undo Monkbot (talk \| contribs) Bots 3,695,952 edits m Task 18 (cosmetic): eval 2 templates: hyphenate params (3×); Tag: AWB Next edit →
Line 6: An example of MIMD system is [[Xeon Phi\|Intel Xeon Phi]], descended from [[Larrabee (microarchitecture)\|Larrabee]] microarchitecture.<ref>http://perilsofparallel.blogspot.gr/2008/09/larrabee-vs-nvidia-mimd-vs-simd.html</ref> These processors have multiple processing cores (up to 61 as of 2015) that can execute different instructions on different data. Most parallel computers, as of 2013, are MIMD systems.<ref>{{cite web\|url=http://software.intel.com/en-us/articles/mimd \|title=Archived copy \|~~accessdate~~access-date=2013-10-16 \|url-status=dead \|~~archiveurl~~archive-url=https://web.archive.org/web/20131016215430/http://software.intel.com/en-us/articles/mimd \|~~archivedate~~archive-date=2013-10-16 }}</ref> ==Shared memory model==

Multiple instruction, multiple data: Difference between revisions