SystemC: differenze tra le versioni
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The language thus offered has semantical similarities to [[VHDL]] and [[Verilog]], but may be said to have a syntactical overhead compared to these. On the other hand, greater freedom of expressiveness is offered in return, like [[Object-oriented programming | object oriented design partitioning]], template classes and [[dynamic memory allocation]]. Which is more: SystemC is ''both'' a description language ''and'' a simulation kernel. The code written will compile together with the library's simulation kernel to give an executable that behaves like the described model when it is run. The performance of this simulation kernel is not to be compared with that of commercial VHDL/Verilog simulators at the present.
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* [[27 settembre]] [[1999]]: annunciata ''Open SystemC Initiative''
* [[1 marzo]] [[2000]]: rilasciata SystemC v0.91
* [[28 marzo]] [[2000]]: rilasciata SystemC v1.0
* [[1 febbraio]] [[2001]]: rilasciate specifiche del SystemC v2.0 ed il [[codice sorgente]] della v1.2 Beta
* 2000/03/01 SystemC V0.91 released▼
* [[3 giugno]] [[2003
* [[6 giugno]] [[2005
* [[12 dicembre]] [[2005]]: [[Institute of Electrical and Electronics Engineers|IEEE]] approva lo [[standard]] IEEE 1666-2005 per il SystemC
▲* 2003/06/03 SystemC 2.0.1 LRM (language reference manual) released
▲* 2005/06/06 SystemC 2.1 LRM and TLM 1.0 transaction-level modeling standard released
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SystemC was originally developed by Synopsys, Inc., an Electronic Design Automation (EDA) company, to act as the modeling foundation for forthcoming system simulation and synthesis tools. A number of Synopsys' end-users suggested that the only way a modeling environment like SystemC would be adopted broadly, would be as an open source project. Synopsys teamed with a number of large electronics companies, ARM Ltd. and CoWare to launch SystemC in 1999. The chief competitor at the time was another C++ based open source package offered by a small startup called CynApps which later became Forte Design Automation. In June 2000, a standards group know as the Open SystemC Initiative was formed to provide an industry neutral organization to host SystemC activities and to allow Synopsys' largest competitors, Cadence and Mentor Graphics, democratic representation in SystemC development.▼
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▲, Inc., an Electronic Design Automation (EDA) company, to act as the modeling foundation for forthcoming system simulation and synthesis tools. A number of Synopsys' end-users suggested that the only way a modeling environment like SystemC would be adopted broadly, would be as an open source project. Synopsys teamed with a number of large electronics companies, ARM Ltd. and CoWare to launch SystemC in 1999. The chief competitor at the time was another C++ based open source package offered by a small startup called CynApps which later became Forte Design Automation. In June 2000, a standards group know as the Open SystemC Initiative was formed to provide an industry neutral organization to host SystemC activities and to allow Synopsys' largest competitors, Cadence and Mentor Graphics, democratic representation in SystemC development.
== Caratteristiche ==
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=== Canali ===
I canali sono gli elementi che permettono la comunicazione nel SystemC. Possono essere sia semplici cavi o complessi sistemi di comunicazione, come [[FIFO]] o [[bus (informatica)|bus]]
Canali elementari:
* signal
* buffer
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=== Interfacce ===
Le porte usano le interfacce per comunicare con i canali.
=== Eventi ===
Permette la sincronizzazione fra i processi.
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Il SystemC
* sc_int<> 64-bit signed integer
* sc_uint<> 64-bit unsigned integer
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* sc_biguint<> arbitrary precision unsigned integer
Tipi logici:
* sc_bit 2-valued single bit
* sc_logic 4-valued single bit
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* sc_fix untemplated signed fixed point
* sc_ufix untemplated unsigned fixed point
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== Esempio ==
Esempio di codice per un sommatore:
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