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Line 67: ==Implementations== * [[Cisco]] PXF network processor is internally organized as systolic array.<ref>{{cite web\|title=Cisco 10000 Series Router Performance Routing Engine Installation\|url=https://www.cisco.com/en/US/products/hw/routers/ps133/prod_installation_guide09186a0080525aba.html#wp48065\|~~accessdate~~access-date=3 August 2020}}</ref> * Google’s [[Tensor Processing Unit\|TPU]] is also designed around a systolic array. * Paracel FDF4T TestFinder text search system<ref name="FDF4">{{cite web\|title=About Paracel\|url=http://brandprosgroup.com/pages/first/websites/paracel/data/html/about_paracel2.html\|website=brandprosgroup.com\|publisher=Paracel\|~~accessdate~~access-date=4 May 2018}}</ref> * Paracel FDF4G GeneMatcher Biological (DNA and Protein) search system * Inferentia chip at [[Amazon Web Services]] <ref>{{cite web\|title=Announcing availability of Inf1 instances in Amazon SageMaker for high performance and cost-effective machine learning inference\|url=https://aws.amazon.com/blogs/aws/amazon-ecs-now-supports-ec2-inf1-instances/\|~~accessdate~~access-date=15 August 2020}}</ref> ==See also==

Systolic array: Difference between revisions