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[[File:64K DRAM Shmoo Plot-abnormal.png|thumb|Abnormal shmoo plot]]
[[File:Figure 5. Shmoo plots with test period power supply test on a few FE-I4 devices.png|thumb|Two-colored Shmoo plots for comparing good and bad devices]]
[[File:Shmoo_procedure.jpg|thumb|Shmooing procedure to optimise ROS in an IBM S/360 CPU]]
Automated test equipment have traditionally generated a two-dimensional, [[ASCII]] form of the shmoo plot that uses an "X" to represent functional points and blank space for non-functional points. In modern times plots with two colors (e.g. red/green) or even multi colored plots in form of digital spread sheet documents and alike became also common, even if the traditional form is still in use.<ref>[https://www.researchgate.net/publication/305762550_A_28-nm_484-fJwritecycle_650-fJreadcycle_8T_Three-Port_FD-SOI_SRAM_for_Image_Processor Energy optimization for an 28 nm sized storage semiconductor using ASCII Shmoo plots for read and write metrics, dated 2016]</ref> For testing efficiency sometimes only the border of interest (where a certain value changes its state) is backed up with data in the diagrams thus (often reasonably) assuming the areas outside those transition will stay at those state.<ref>[https://www.edn.com/electronics-blogs/day-in-the-life-of-a-chip-designer/4438729/Silicon-debug-challenges-and-guidelines Examples for thinned out, multi-color Shmoo diagrams, dated 2015]</ref>
If sufficiently-wide ranges of the two independent variables were to be tested, a normal shmoo plot would show an operating envelope of some shape not unlike Al Capp's [[Shmoo]], but in practice, this might damage the [[device under test]], and finer-grained views are of much more interest, particularly focusing on published component margins (e.g., - 5% Vcc). When this is done, the operating envelope typically extends to the border of the plot in one or more directions.
One example of such “shmooing” is the procedure for optimising the two operating variables of the Read Only Storage (ROS) in the [[IBM S/360]] Model 65 Central Processing Unit (CPU). While the CPU is running a diagnostic test program the ROS bias voltage and time delay are varied and the points where the ROS generates errors are manually plotted on a graphical shmoo plot (see illustration). To pass the test the shmoo plot must be large enough to contain a rectangle which represents the minimum permissible error-free range of bias voltage and time delay. The optimum ROS bias voltage and time delay will be indicated by a point at the centre of the rectangle.
Sometimes a shmoo plot has an unusual and surprising shape, and while it is difficult to determine the exact cause, it is sometimes due to some unusual defect (perhaps in only part of a circuit) coupled with otherwise normal operation. In other cases, it might be an artifact of the electrical testing setup or the test program used, in particular a [[race condition]]. As such, a shmoo plot can be a useful test setup verification tool.
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