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Local APICs (LAPICs) manage all external interrupts for some specific processor in an SMP system. In addition, they are able to accept and generate [[inter-processor interrupt]]s (IPIs) between LAPICs. LAPICs may support up to 224 usable [[interrupt]] vectors from an I/O APIC. Vector numbers 0 to 31, out of 0 to 255, are reserved for exception handling by x86 processors.
All Intel processors starting with the P5 microarchitecture ([[P54C]]) have a built-in local APIC.<ref name="Mueller2011">{{cite book|author=Scott M. Mueller|title=Upgrading and Repairing PCs|year=2011|publisher=Que Publishing|isbn=978-0-13-268218-3|page=242|edition=20th}}</ref><ref name="timer" /> However, if the local APIC is disabled in a P5 processor, it cannot be re-enabled by software; this limitation no longer exists in the [[P6 (microarchitecture)|P6 processors]] and later ones.<ref name="timer" />
The [[Message Signaled Interrupts]] (MSI) feature of the PCI 2.2 and later specifications cannot be used without the local APIC being enabled.<ref name="up">{{cite web|url=http://msdn.microsoft.com/en-us/windows/hardware/gg462964.aspx|title=Windows Hardware Dev Center|website=msdn.microsoft.com}}</ref> Use of MSI obviates the need for an I/O APIC. Additionally, up to 224 interrupts are supported in MSI mode, and IRQ sharing is not allowed.<ref name="msi"/>
=== APIC timer ===
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