Revision as of 10:24, 13 February 2021 edit 49.206.119.9 (talk) →Execute ← Previous edit		Revision as of 21:03, 25 February 2021 edit undo 2602:306:cf72:5bc0:b5dc:117f:d0cc:80d0 (talk) →Memory access: improved wording Next edit →
Line 41: ===Memory access=== If data memory needs to be accessed, it is done so in this stage. During this stage, single cycle latency instructions simply have their results forwarded to the next stage. This forwarding ensures that both one and two cycle instructions always write their results in the same stage of the pipeline so that just one write port to the register file can be used, and it is always available.

Classic RISC pipeline: Difference between revisions