Multiple instruction, multiple data: Difference between revisions

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==Shared memory model==

TheIn shared memory model the processors are all connected to a "globally available" memory, via either [[software]] or hardware means. The [[operating system]] usually maintains its [[memory coherence]].<ref name="Ibaroudene-slides">Ibaroudene, Djaffer. "Parallel Processing, EG6370G: Chapter 1, Motivation and History." Lecture Slides. [[St. Mary's University, Texas|St Mary's University]], [[San Antonio, Texas]]. Spring 2008.</ref>

From a programmer's point of view, this memory model is better understood than the distributed memory model. Another advantage is that memory coherence is managed by the operating system and not the written program. Two known disadvantages are: scalability beyond thirty-two processors is difficult, and the shared memory model is less flexible than the distributed memory model.<ref name="Ibaroudene-slides"/>

There are many examples of shared memory (multiprocessors): UMA ([[Uniformuniform Memorymemory Accessaccess]]), COMA ([[Cache-only Onlymemory Memoryarchitecture|cache-only Accessmemory access]]).<ref name=tanenbaum>{{cite book|author=Andrew S. Tanenbaum|author-link=Andrew S. Tanenbaum|title=Structured Computer Organization|pages=559–585|publisher=Prentice-Hall|year=1997|url=http://cwx.prenhall.com/bookbind/pubbooks/tanenbaum2/chapter0/deluxe.html|edition=4|isbn=978-0130959904|access-date=2013-03-15|archive-url=https://web.archive.org/web/20131201035507/http://cwx.prenhall.com/bookbind/pubbooks/tanenbaum2/chapter0/deluxe.html|archive-date=2013-12-01|url-status=dead}}</ref>

===Bus-based===

MIMD machines with shared memory have processors which share a common, central memory. In the simplest form, all processors are attached to a bus which connects them to memory. This means that every machine with shared memory shares a specific CM, common bus system for all the clients.

This means that every machine with shared memory shares a specific CM, common bus system for all the clients.

For example, if we consider a bus with clients A, B, C connected on one side and P, Q, R connected on the opposite side,

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=== Hierarchical ===

MIMD machines with hierarchical shared memory use a hierarchy of buses (as, for example, in a "[[Fatfat tree]]") to give processors access to each other's memory. Processors on different boards may communicate through inter-nodal buses. Buses support communication between boards. With this type of architecture, the machine may support over nine thousand processors.

== Distributed memory ==