MIPS architecture processors: Difference between revisions

Content deleted Content added
Small WP:EoS WP:TERSE WP:COPYEDITs: clarify, WP:IDIOM > WP:FORMAL. WP:LINKs: adds, updates, fix-cut needless WP:PIPEs (WP:NOPIPEs). WP:BADEMPHASIS MOS:BOLDs > WP:ITALICs. Nonlead-word nonproper noun MOS:CAPS > sentence case. MOS:FIRSTABBReviations define before WP:ABBRs in parentheses. WP:REFerences: plain text + inline WP:EXTernal links > WP:CITation, parameters: adds, fills from source, reorders, cut repeat terms.
No edit summary
Line 12:
The first MIPS microprocessor, the ''[[R2000 (microprocessor)|R2000]]'', was announced in 1985. It added multiple-cycle multiply and divide instructions in a somewhat independent on-chip unit. New instructions were added to retrieve the results from this unit back to the [[processor register]] file; these result-retrieving instructions were interlocked.
 
The R2000 could be booted either [[Endianness|''big-endian'' or ''little-endian'']]. It had thirty-one 32-bit general purpose registers, but no [[status register]] (''condition code register'' (CCR), the designers considered it a potential bottleneck), a feature it shares with the [[AMD 29000]] and, the [[DEC Alpha]], and [[RISC-V]]. Unlike other registers, the [[program counter]] is not directly accessible.
 
The R2000 also had support for up to four co-processors, one of which was built into the main ''[[central processing unit]]'' (CPU) and handled exceptions, traps and memory management, while the other three were left for other uses. One of these could be filled by the optional ''R2010'' [[floating-point unit]] (FPU), which had thirty-two 32-bit registers that could be used as sixteen 64-bit registers for double-precision.