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Indolering (talk | contribs) Added link to Iron law of performance, because I know it has something to do with RISC pipelining but not enough to comment intelligently. |
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Another strategy to handle suspend/resume is to reuse the exception logic. The machine takes an exception on the offending instruction, and all further instructions are invalidated. When the cache has been filled with the necessary data, the instruction that caused the cache miss restarts. To expedite data cache miss handling, the instruction can be restarted so that its access cycle happens one cycle after the data cache is filled.
== See
* [[Iron law of processor performance]]
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