Single-electron transistor: Difference between revisions

Revision as of 08:04, 15 January 2021

Revision as of 23:18, 23 March 2021

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A '''single-electron transistor''' ('''SET''') is a sensitive electronic device based on the [[Coulomb blockade]] effect. In this device the electrons flow through a tunnel junction between source/drain to a [[quantum dot]] (conductive island). Moreover, the electrical potential of the island can be tuned by a third electrode, known as the gate, which is capacitively coupled to the island. The conductive island is sandwiched between two tunnel junctions,

<ref>{{cite journal|last1=Mahapatra|first1=S.|last2=Vaish|first2=V.|last3=Wasshuber|first3=C.|last4=Banerjee|first4=K.|last5=Ionescu|first5=A.M.|title=Analytical Modeling of Single Electron Transistor for Hybrid CMOS-SET Analog IC Design|journal=IEEE Transactions on Electron Devices|volume=51|issue=11|year=2004|pages=1772–1782|issn=0018-9383|doi=10.1109/TED.2004.837369|bibcode=2004ITED...51.1772M|s2cid=15373278}}</ref> which are modeled by a capacitor (<math>C_{\rm D}</math> and <math>C_{\rm S}</math>) and a resistor (<math>R_{\rm D}</math> and <math>R_{\rm S}</math>) in parallel.

== History ==

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When [[David Thouless]] pointed out in 1977 that the size of a conductor, if made small enough, will affect the electronic properties of the conductor, a new subfield of condensed matter physics was started.<ref>{{cite journal |last1=Thouless |first1=David J. |author-link=David J. Thouless| title=Maximum Metallic Resistance in Thin Wires |journal=Phys. Rev. Lett. |volume=39 |issue=18 |pages=1167–1169 |year=1977 |doi=10.1103/PhysRevLett.39.1167|bibcode=1977PhRvL..39.1167T }}</ref> The research that followed during the 1980s was known as the [[mesoscopic physics]], based on the submicron-size systems investigated.<ref>{{cite journal|last1=Al'Tshuler|first1=Boris L.|last2=Lee|first2=Patrick A.|title=Disordered electronic systems|journal=Physics Today|volume=41|issue=12|year=1988|pages=36–44|doi=10.1063/1.881139|bibcode=1988PhT....41l..36A}}</ref> This was the starting point of the research related to the single-electron transistor.

The first single-electron transistor based on the Coulomb blockade was reported in 1986 by Soviet scientists {{ill|K. K. Likharev|ru|Лихарев, Константин Константинович}} and D. V. Averin.<ref name=":1">{{Cite journal|lastlast1=Averin|firstfirst1=D. V.|last2=Likharev|first2=K. K.|date=1986-02-01|title=Coulomb blockade of single-electron tunnelling, and coherent oscillations in small tunnel junctions|journal=Journal of Low Temperature Physics|language=en|volume=62|issue=3–4|pages=345–373|doi=10.1007/BF00683469|issn=0022-2291|bibcode=1986JLTP...62..345A|s2cid=120841063}}</ref> A couple of years later, T. Fulton and G. Dolan at Bell Labs in the US fabricated and demonstrated how such a device works.<ref>{{cite web|url=https://physicsworld.com/a/single-electron-transistors/|title=Single-electron transistors|date=1998-09-01|access-date=2019-09-17|publisher=Physics World}}</ref> In 1992 [[Marc A. Kastner]] demonstrated the importance of the [[energy levels]] of the quantum dot.<ref>{{cite journal|last1=Kastner|first1=M. A.|date=1992-07-01|title=The single-electron transistor|journal=Rev. Mod. Phys.|volume=64|issue=3|pages=849–858|doi=10.1103/RevModPhys.64.849|bibcode=1992RvMP...64..849K}}</ref> In the late 1990s and early 2000s, Russian physicists S. P. Gubin, V. V. Kolesov, E. S. Soldatov, A. S. Trifonov, V. V. Khanin, G. B. Khomutov, and S. A. Yakovenko were the first ones to ever make a molecule based SET operational at room temperature.<ref>{{cite journal|last1=Gubin|first1=S. P.|last2=Gulayev|first2=Yu V.|last3=Khomutov|first3=G. B.|last4=Kislov|first4=V. V.|last5=Kolesov|first5=V. V.|last6=Soldatov|first6=E. S.|last7=Sulaimankulov|first7=K. S.|last8=Trifonov|first8=A. S.|title=Molecular clusters as building blocks for nanoelectronics: the first demonstration of a cluster single-electron tunnelling transistor at room temperature|doi=10.1088/0957-4484/13/2/311|journal=Nanotechnology|year=2002|pages=185–194|volume=13|issue=2|bibcode=2002Nanot..13..185G}}.</ref>

== Relevance ==

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[[File:SETFET schematic.jpg|thumb|Hybrid SET-FET circuit.]]

The level of the electrical current of the SET can be amplified enough to work with available [[CMOS]] technology by generating a hybrid SET-[[field-effect transistor|FET]] device.<ref name="IonescuMahapatra2004">{{cite journal|last1=Ionescu|first1=A.M.|last2=Mahapatra|first2=S.|last3=Pott|first3=V.|title=Hybrid SETMOS Architecture With Coulomb Blockade Oscillations and High Current Drive|journal=IEEE Electron Device Letters|volume=25|issue=6|year=2004|pages=411–413|issn=0741-3106|doi=10.1109/LED.2004.828558|bibcode=2004IEDL...25..411I|s2cid=42715316}}</ref><ref name="AmatBausells2017">{{cite journal|last1=Amat|first1=Esteve|last2=Bausells|first2=Joan|last3=Perez-Murano|first3=Francesc|title=Exploring the Influence of Variability on Single-Electron Transistors Into SET-Based Circuits|journal=IEEE Transactions on Electron Devices|volume=64|issue=12|year=2017|pages=5172–5180|issn=0018-9383|doi=10.1109/TED.2017.2765003|bibcode=2017ITED...64.5172A|s2cid=22082690}}</ref>

The EU funded, in 2016, project IONS4SET (#688072)<ref>{{cite web|url=http://www.ions4set.eu|title=IONS4SET Website|access-date=2019-09-17}}</ref> looks for the manufacturability of SET-FET circuits operative at room temperature. The main goal of this project is to design a SET-manufacturability process-flow for large-scale operations seeking to extend the use of the hybrid Set-CMOS architectures. To assure room temperature operation, single dots of diameters below 5&nbsp;nm have to be fabricated and located between source and drain with tunnel distances of a few nanometers.<ref name="KlupfelBurenkov2016">{{cite book|last1=Klupfel|first1=F. J.|title=2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)|last2=Burenkov|first2=A.|last3=Lorenz|first3=J.|chapter=Simulation of silicon-dot-based single-electron memory devices|year=2016|pages=237–240|doi=10.1109/SISPAD.2016.7605191|isbn=978-1-5090-0818-6|s2cid=15721282}}</ref> Up to now there is no reliable process-flow to manufacture a hybrid SET-FET circuit operative at room temperature. In this context, this EU project explores a more feasible way to manufacture the SET-FET circuit by using pillar dimensions of approximately 10&nbsp;nm.<ref name="Xu2019">{{cite arXiv |eprint=1906.09975v2|last1=Xu|first1=Xiaomo|title=Morphology modifcation of Si nanopillars under ion irradiation at elevated temperatures: Plastic deformation and controlled thinning to 10 nm|last2=Heinig|first2=Karl-Heinz|last3=Möller|first3=Wolfhard|last4=Engelmann|first4=Hans-Jürgen|last5=Klingner|first5=Nico|last6=Gharbi|first6=Ahmed|last7=Tiron|first7=Raluca|author8=Johannes von Borany|last9=Hlawacek|first9=Gregor|class=physics.app-ph|year=2019}}</ref>

== See also ==