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The QPI is an element of a system architecture that Intel calls the ''QuickPath architecture'' that implements what Intel calls ''QuickPath technology''.<ref>{{cite web |title=Intel Demonstrates Industry's First 32nm Chip and Next-Generation Nehalem Microprocessor Architecture |url= http://www.intel.com/pressroom/archive/releases/20070918corp_a.htm?iid=tech_arch_32nm+body_pressrelease |access-date=2007-12-31 |archive-url=https://web.archive.org/web/20080102101316/http://www.intel.com/pressroom/archive/releases/20070918corp_a.htm?iid=tech_arch_32nm+body_pressrelease |archive-date=2008-01-02}}</ref> In its simplest form on a single-processor motherboard, a single QPI is used to connect the processor to the IO Hub (e.g., to connect an [[Intel Core i7]] to an [[Intel X58|X58]]). In more complex instances of the architecture, separate QPI link pairs connect one or more processors and one or more IO hubs or routing hubs in a network on the motherboard, allowing all of the components to access other components via the network. As with HyperTransport, the QuickPath Architecture assumes that the processors will have integrated [[memory controller]]s, and enables a [[non-uniform memory access]] (NUMA) architecture.
Each QPI comprises two 20-lane point-to-point data links, one in each direction ([[full duplex]]), with a separate clock pair in each direction, for a total of 42 signals. Each signal is a [[differential signaling|differential pair]], so the total number of pins is 84. The 20 data lanes are divided onto four "quadrants" of 5 lanes each. The basic unit of transfer is the 80-bit [[flit (computer networking)|flit]], which is transferred in two clock cycles (four 20-bit transfers, two per clock tick.) The 80-bit flit has 8 bits for error detection, 8 bits for "link-layer header", and 64 bits for data. QPI bandwidths are advertised by computing the transfer of 64 bits (8 bytes) of data every two clock cycles in each direction.<ref name="realworld">{{cite web |title= The Common System Interface: Intel's Future Interconnect |work= Real World Tech |author= David Kanter |date= August 28, 2007 |url= http://www.realworldtech.com/common-system-interface/ |access-date= August 14, 2014 }}</ref>
Although the initial implementations use single four-quadrant links, the QPI specification permits other implementations. Each quadrant can be used independently. On high-reliability servers, a QPI link can operate in a degraded mode. If one or more of the 20+1 signals fails, the interface will operate using 10+1 or even 5+1 remaining signals, even reassigning the clock to a data signal if the clock fails.<ref name="realworld"/> The initial Nehalem implementation used a full four-quadrant interface<!-- what is that? --> to achieve 25.6 GB/s, which provides exactly double the theoretical bandwidth of Intel's 1600 MHz FSB used in the X48 chipset.
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