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m →Implementation: Sorry, on second thought "which therefore communicate externally" works much better than "and therefore [they] communicate externally". |
m →Implementation: Nope, apparently not finished yet, as the last bit now should actually be two paragraphs, with the second to last being another stand alone topic sentence. |
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In post-2009 single-socket chips starting with Lynnfield, Clarksfield, Clarkdale and Arrandale, the traditional [[Northbridge (computing)|northbridge]] functions are integrated into these processors, which therefore communicate externally via the slower [[Direct Media Interface|DMI]] and PCI Express interfaces.
Thus, there is no need to incur the expense of exposing the (former) front-side bus interface via the processor socket.<ref>Lily Looi, Stephan Jourdan, [http://www.hotchips.org/wp-content/uploads/hc_archives/hc21/2_mon/HC21.24.400.ClientProcessors-Epub/HC21.24.442.Looi-Intel_NhmClient_Hotchips2009b.pdf Transitioning the Intel® Next Generation Microarchitectures (Nehalem and Westmere) into the Mainstream], Hot Chips 21, August 24, 2009</ref>
Although the core–uncore QPI link is not present in desktop and mobile [[Sandy Bridge]] processors (as it was on Clarkdale, for example), the internal ring interconnect between on-die cores is also based on the principles behind QPI, at least as far as [[cache coherency]] is concerned.<ref name="hotchips-2nd-gen" />{{rp|10}} ==Frequency specifications==
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