Locality of reference: Difference between revisions

Revision as of 00:46, 18 April 2021

Revision as of 12:34, 20 April 2021

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Typical memory hierarchy (access times and cache sizes are approximations of typical values used {{As of|2013|lc=on}} for the purpose of discussion; actual values and actual numbers of levels in the hierarchy vary):

* [[CPU register]]s (8-2568–256 registers) – immediate access, with the speed of the innermost core of the processor

* L1 [[CPU cache]]s (32 KiB to 512 [[KiB]]) – fast access, with the speed of the innermost memory bus owned exclusively by each core

* L2 CPU caches (128 KiB to 24 [[MiB]]) – slightly slower access, with the speed of the [[memory bus]] shared between twins of cores

* L3 CPU caches (2 MiB to 32 [[MiB]]) – even slower access, with the speed of the memory bus shared between even more cores of the same processor

* Main [[physical memory]] ([[random-access memory|RAM]]) (256 MiB to 64 [[GiB]]) – slow access, the speed of which is limited by the spatial distances and general hardware interfaces between the processor and the memory modules on the [[motherboard]]

* Disk ([[virtual memory]], [[file system]]) (1 GiB to 256 [[TiB]]) – very slow, due to the narrower (in bit width), physically much longer data channel between the main board of the computer and the disk devices, and due to the extraneous software protocol needed on the top of the slow hardware interface

* Remote memory (other computers or the cloud) (practically unlimited) – speed varies from very slow to extremely slow