Programmable interrupt controller: Difference between revisions

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{{more footnotes|date=September 2013}}

In [[computing]], a '''programmable interrupt controller''' ('''PIC''') is an [[integrated circuit]] that helps a [[microprocessor]] (or [[CPU]]) handle [[Interrupt request (PC architecture)|interrupt requests]] (IRQ) coming from multiple different sources (like external I/O devices) which may occur simultaneously.<ref>{{cite journal|title=A Revisitation of Kernel Synchronization Schemes

|urlauthors=https://static.usenix.org/publications/library/proceedings/ana97/full_papers/small/small.html}}</ref>Christopher It helps prioritize IRQs so that the CPU switches execution to the most appropriate [[interrupt handler]] (ISR) after the PIC assesses the IRQ's relative priorities.Small Common modes of interrupt priority include hard priorities, rotating priorities, and cascading priorities.{{Citation needed|date=July 2011}} PICs often allow mapping input to outputs in a configurable way. On the [[PC architecture]] PIC are typically embedded into a [[Southbridge (computing)|southbridge chips]] whose internal architecture is defined by the chipset vendor's standards.

|authors=Christopher Small and Stephen Manley

|url=https://static.usenix.org/publications/library/proceedings/ana97/full_papers/small/small.html}}</ref> It helps prioritize IRQs so that the CPU switches execution to the most appropriate [[interrupt handler]] (ISR) after the PIC assesses the IRQ's relative priorities. Common modes of interrupt priority include hard priorities, rotating priorities, and cascading priorities.{{Citation needed|date=July 2011}} PICs often allow mapping input to outputs in a configurable way. On the [[PC architecture]] PIC are typically embedded into a [[Southbridge (computing)|southbridge chips]] whose internal architecture is defined by the chipset vendor's standards.

==Common features==