FPGA prototyping: Difference between revisions

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#Running a SoC design on FPGA prototype is a reliable way to ensure that it is functionally correct. This is compared to designers only relying on [[Electronic circuit simulation|software simulations]] to verify that their hardware design is sound. About a third of all current SoC designs are fault-free during first silicon pass, with nearly half of all re-spins caused by functional logic errors.<ref name ="soc">{{Cite web |url=http://www.soccentral.com/results.asp?CatID=596&EntryID=30794 |title=Archived copy |access-date=October 9, 2012 |archive-url=https://archive.is/20130202104923/http://www.soccentral.com/results.asp?CatID=596&EntryID=30794 |archive-date=February 2, 2013 |url-status=dead }}</ref> A single prototyping platform can provide verification for hardware, firmware, and application software design functionality before the first silicon pass.<ref>{{Cite web|url=http://www.tayden.com/publications/Nanometer%20Prototyping.pdf|title=Nanometer prototyping|last=Rittman|first=Danny|date=2006-01-05|website=Tayden Design|access-date=2018-10-07}}</ref>

#[[Time to market|Time-to-Marketmarket]] (TTM) is reduced from FPGA prototyping: In today's technological driven society, new products are introduced rapidly, and failing to have a product ready at a given [[market window]] can cost a company a considerable amount of [[revenue]].<ref name="reason">{{Cite web|url=http://www.design-reuse.com/articles/13550/fpga-prototyping-to-structured-asic-production-to-reduce-cost-risk-ttm.html|title=FPGA Prototyping to Structured ASIC Production to Reduce Cost, Risk & TTM|website=Design And Reuse|access-date=2018-10-07}}</ref> If a product is released too late of a market window, then the product could be [[Obsolescence|rendered useless]], costing the company its investment capital in the product. After the design process, FPGAs are ready for production, while [[Standard cell|standard cell ASICs]] take more than six months to reach production.<ref name = reason/>

#Development Costcost: Development cost of 90-nm ASIC/SoC design tape-out is around $20 million, with a mask set costing over $1 million alone.<ref name= soc/> Development costs of 45-nm designs are expected to top $40 million. With increasing cost of mask sets, and the continuous decrease of IC size, minimizing the number of re-spins is vital to the development process.

==Design for prototyping==

'''Design for Prototypingprototyping'''<ref>{{cite web|url=http://www.newelectronics.co.uk/electronics-technology/prototyping-system-designs-on-fpgas/32395/|title=Prototyping System Designs on FPGAs|date=2011-03-22|publisher=New Electronics|accessdate=2011-03-22}}</ref> ('''DFP''') refers to designing systems that are amenable to [[prototyping]]. Many of the obstacles facing development teams who adopt FPGA prototypes can be distilled down to three "laws":

* SoCs are larger than FPGAs

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System RTL designs or netlists will have to be partitioned onto each FPGA to be able to fit the design onto the prototyping platform.<ref>{{Cite web |url=http://www.electronicsweekly.com/Articles/20/12/2007/42539/fpga-prototyping-its-about-the-software.htm |title=Archived copy |access-date=October 9, 2012 |archive-url=https://archive.is/20130122001104/http://www.electronicsweekly.com/Articles/20/12/2007/42539/fpga-prototyping-its-about-the-software.htm |archive-date=January 22, 2013 |url-status=dead }}</ref> This introduces new challenges for the engineer since manual partitioning requires tremendous effort and frequently results in poor speed (of the design under test).<ref name ="Aldec">[http://www.aldec.com/en/downloads/private/284 "Aldec and Xilinx Co-Authored White Paper "HES-7 ASIC Prototyping"], Registration Required</ref> If the number or partitions can be reduced or the entire design can be placed onto a single FPGA, the implementation of the design onto the prototyping platform becomes easier.

===Balance FPGA Resourcesresources Whilewhile Creatingcreating Designdesign Partitionspartitions===

When creating circuit partitions, engineers should first observe the available resources the FPGA offers, since the design will be placed onto the FPGA fabric.<ref name="Aldec" /> The architecture of each FPGA is dependent on the manufacturer, but the main goal in design partitioning is to have an even balance of FPGA resource utilization. Various FPGA resources include [[Lookup table|lookup tables]] (LUTs), [[D flip-flops]], block [[Random-access memory|RAMs]], [[Digital signal processor|digital signal processors]] (DSPs), clock buffers, etc. Prior to balancing the design partitions, it is also valuable to the user to perform global [[logic optimization]] to remove any redundant or unused logic. A typical problem that arises with creating balanced partitions is that it may lead to timing or resource conflict if the cut is on many signal lines. To have a fully optimized partitioning strategy, the engineer must consider issues such as timing/power constraints and placement and routing while still maintaining a balanced partition amongst the FPGAs. Strictly focusing on a single issue during a partition may create several issues in another.

===Placing and Routingrouting Partitionspartitions===

In order to achieve optimal place and routing for partitioned designs, the engineer must focus on FPGA pin count and inter-FPGA signals. After partitioning the design into separate FPGAs, the number of inter-FPGA signals must not to exceed the pin count on the FPGA.<ref>http://www.fpga-faq.com/FAQ_Pages/prototyping.pdf</ref> This is very difficult to avoid when circuit designs are immense, thus signals must utilize strategies such as [[time-division multiplexing]] (TDM) which multiple signals can be transferred over a single line.<ref>{{Cite web|url=http://www.inetdaemon.com/tutorials/telecom/t-carrier/time-division_multiplexing.shtml|title=Time-Division Multiplexing|website=www.inetdaemon.com|language=en-US|access-date=2018-10-08}}</ref> These multiple signals, called sub-channels, take turns being transferred over the line over a time slot. When the TDM ratio is high, the bus clock frequency has to be reduced to accommodate time slots for each sub-channel. By reducing the clock frequency the throughput of the system is hindered.<ref name=Aldec/>

===Timing Requirementsrequirements===

System designs usually [[Clock ___domain crossing|encompass several clock domains]] with signals traversing separate domains.<ref name="Aldec" /> On-board [[Clock generator|clock oscillators]] and global clock lines usually mitigate these issues, but sometimes these resources may be limited or not fulfill all design requirements. Internal clocks should be implemented within FPGA devices since clock line and clock buffers connections are limited between FPGAs. Internal clocked designs which are partitioned across multiple FPGAs should replicate the clock generator within the FPGA, ensuring a low clock skew between inter-FPGA signals. In addition, any gated clock logic should be transformed to clock enables to reduce skew while operating at high clock frequencies.

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==Debugging==

One of the most difficult and time-consuming tasks in FPGA prototyping is debugging system designs. The term coined for this is "FPGA Hellhell".<ref>{{Cite web|url=https://zipcpu.com/blog/2017/05/19/fpga-hell.html|title=FPGA Hell|website=zipcpu.com|access-date=2019-11-05}}</ref><ref>{{Cite web|url=http://www.rocketmanrc.com/downloads/MakerFaire2019FPGAsPresentation.pdf|title=Getting Started with FPGAs|last=|first=|date=|website=|url-status=live|archive-url=|archive-date=|access-date=}}</ref> Debugging has become more difficult and time-consuming with the emergence of large, complex ASICs and SoC designs. To debug an FPGA prototype, probes are added directly to the RTL design to make specific signals available for observation, synthesized and downloaded to the FPGA prototype platform.

A number of standard debugging tools are offered by FPGA vendors including ChipScope and SignalTAP. These tools can probe a maximum of 1024 signals and require extensive LUT and memory resources. For SoC and other designs, efficient debugging often requires concurrent access to 10,000 or more signals. If a bug is not able to be captured by the original set of probes, gaining access to additional signals results in a “go home for the day” situation. This is due to long and complex CAD flows for synthesis and place and route that can require from 8 to 18 hours to complete.