A '''compressed instruction set''', or simply '''compressed instructions''', are a variation on a [[microprocessor]]'s [[instruction set architecture]] (ISA) that allows instructions to be represented in a more compact format. In most real-world examples, compressed instructions are 16 bits long in a processor that would otherwise use 32-bit instructions. It is distinct from the concept of [[variable length instructions]], where any instruction can have any length; in a compressed set the instructions are alternative forms for existing 32-bit versions.
The concept was originally introduced in the 1980s by [[Hitachi]] as a way to improve the [[code density]] of their [[SuperH]] [[RISC]] processor design as it moved from a 16-bit to 32-bit implementation. The new design had two instruction sets, one giving access to the entire ISA of the new design, and therebya smaller 16-bit set known as SHcompact that allowallowed programs to run in smaller amounts of [[main memory]]. Today these smaller instructions are known as SHcompact. As memory of even the smallest systems is now [[order-of-magnitude|orders of magnitude]] larger, this is no longer the main concern; today the advantage is that it reduces the number of accesses to main memory and thereby reduces energy use in [[mobile device]]s. Hitachi's patents were licensed by [[Arm Ltd.]] for their processors, where it was known as "Thumb". Similar systems are found in MIPS16e, and[[PowerPC]] PowerVLE ISAand [[RISC-V]].
The introduction of [[64-bit computing]] has led to the term no longer being as widely used; these processors generally use 32-bit instructions and are technically a form of compressed ISA, but as they are mostly modified versions of an older 32-bit ISA from a 32-bit version of the same processor family; there is no real compression. The original patents have expired and the concept can be found in a number of modern designs, including the [[RISC-V]], which was designed from the outset to use it.
