Turbo code: Difference between revisions

Revision as of 00:32, 26 March 2021

Revision as of 11:47, 26 July 2021

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This encoder implementation sends three sub-blocks of bits. The first sub-block is the ''m''-bit block of payload data. The second sub-block is ''n/2'' parity bits for the payload data, computed using a recursive systematic [[convolutional code]] (RSC code). The third sub-block is ''n/2'' parity bits for a known [[permutation]] of the payload data, again computed using an RSC code. Thus, two redundant but different sub-blocks of parity bits are sent with the payload. The complete block has {{nowrap|''m'' + ''n''}} bits of data with a code rate of {{nowrap|''m''/(''m'' + ''n'')}}. The [[permutation]] of the payload data is carried out by a device called an [[interleaver]].

Hardware-wise, this turbo code encoder consists of two identical RSC coders, С''C''₁ and ''C''₂, as depicted in the figure, which are connected to each other using a concatenation scheme, called ''parallel concatenation'':

[[File:turbo encoder.svg]]