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| [[University of Cambridge]]
| {{yes|BSD}}
|
| [[MIPS architecture|MIPS]]
| [http://www.cl.cam.ac.uk/research/security/ctsrd/beri/ Project page]
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| Pablo Bleyer
| {{yes}}
|
| Compatible with the PicoBlaze processors
| [http://bleyer.org/pacoblaze PacoBlaze]
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| {{yes|BSD}}
| Wishbone b4, AXI4
| rv32[i/e] [m] [a] [c] [b] [u] [Zfinx] [Zicsr] [Zifencei], RISC-V-compliant, CPU & SoC available, highly customizable, GCC toolchain
| [https://github.com/stnolting/neorv32 GitHub] [https://opencores.org/projects/neorv32 OpenCores]
| VHDL
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| {{Yes}}
|
| [[Manycore processor|Manycore]] [[SPARC|SPARC V9]]
| [http://parallel.princeton.edu/openpiton/specs.html OpenPiton]
| Verilog
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| HT-Lab
| {{yes}}
|
| 8088-compatible CPU in VHDL
| [http://www.ht-lab.com/cpu86.htm cpu86]
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| python/nMigen
|-
| [[
| IBM/OpenPOWER
| {{yes|CC-BY 4.0}}
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| VHDL
|-
| [[
| IBM/OpenPOWER
| {{yes|CC-BY 4.0}}
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| [https://github.com/openpower-cores/a2o A2O @ Github]
| Verilog
|-
| colspan="7" align="center" | ''Other architectures''
|-
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| [[Synopsys#ARC International|ARC International]], [[Synopsys]]
| {{no}}
|
| 16/32/64-bit ISA RISC
| [https://www.synopsys.com/designware-ip/processor-solutions.html DesignWare ARC]
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| Entner Electronics
| {{no}}
|
| 9-bit RISC, very small size, C-programmable
| [http://www.entner-electronics.com/tl/index.php/eric5.html ERIC5]
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| Miguel Angel Ajo Pelayo
| {{yes|MIT}}
|
| PIC12F compatible, program synthesised in gates
| [http://projects.nbee.es/display/IPCORES/SYNPIC12+8bit+RISC+CPU+core nbee.es]
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| Verilog
|-
| [[
| Zylin AS
| {{yes}}
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== See also ==
* [[System on a chip|System-on-a-chip]] (SoC)
** [[Network on a chip|Network-on-a-chip]] (NoC)
* [[Reconfigurable computing]]
** [[Field-programmable gate array]] (FPGA)
* [[VHDL]]
* [[Verilog]]
** [[SystemVerilog]]
* [[Hardware acceleration]]
==References==
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