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The CMOS RAM and the real-time clock have been integrated as a part of the [[Southbridge (computing)|southbridge]] chipset and it may not be a standalone chip on modern motherboards.<ref>https://www.intel.com/Assets/PDF/datasheet/290562.pdf</ref><ref name="100Series">{{cite web|url=http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html |title=Intel 100 Series Chipset Family PCH Datasheet| publisher=Intel |date=August 2015 |access-date=16 April 2016}}</ref> In turn, the southbridge have been integrated into a single [[Platform Controller Hub]].
Today's [[UEFI]] motherboards use [[NVRAM]] to store configuration data (NVRAM is a part of the UEFI flash ROM), but by many [[OEM]]s' design, the UEFI settings are still lost if the CMOS battery fails.<ref>{{Cite web|title=UEFI NVRAM - OSDev Wiki|url=https://wiki.osdev.org/UEFI_NVRAM|access-date=2020-09-11|website=wiki.osdev.org}}</ref><ref>{{Cite book|chapter-url=https://media.springernature.com/original/springer-static/image/chp%3A10.1007%2F978-1-4842-6106-4_4/MediaObjects/488723_1_En_4_Fig6_HTML.png|doi = 10.1007/978-1-4842-6106-4_4|chapter = Firmware Resiliency: Detection|title = Building Secure Firmware|year = 2020|last1 = Yao|first1 = Jiewen|last2 = Zimmer|first2 = Vincent|pages = 115–162|isbn = 978-1-4842-6105-7}}</ref>
==CMOS battery==
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