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The 960MX version of the [[Intel i960]] processors supported load and store instructions with the source or destination being an "access descriptor" for an object, and an offset into the object, with the access descriptor being in a 32-bit register and with the offset computed from a base offset in the next register and from an additional offset and, optionally, an index register specified in the instruction. An access descriptor contains permission bits and a 26-bit object index; the object index is an index into a table of object descriptors, giving an object type, an object length, and a physical address for the object's data, a page table for the object, or the top-level page table for a two-level page table for the object, depending on the object type.<ref>{{cite book|url=http://bitsavers.org/pdf/biin/BiiN_CPU_Architecture_Reference_Man_Jul88.pdf|title=BiiN CPU Architecture Reference Manual|date=July 1998|publisher=BiiN}}</ref>
[[Prime Computer|Prime]], [[Stratus Technologies|Stratus]], [[Apollo Computer|Apollo]], [[IBM System/38]], and [[IBM AS/400]] (including [[IBM i
==x86 architecture==
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