Push–pull output: Difference between revisions

Revision as of 18:03, 10 September 2021

Revision as of 23:30, 10 September 2021

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[[File:7400 Circuit.svg|right|thumb|Circuit of [[Transistor–transistor logic|TTL]] [[NAND gate]] has a 'totem pole output' stage ''(right)'' consisting of two NPN transistors in push pull. When at least one of the inputs is low, transistor ''V''₂ is turned off, ''V''₃ is turned on and ''V''₄ off, pulling output voltage high. When both inputs are high, ''V''₂ is on, ''V''₃ is off and ''V''₄ is turned on, pulling output low.]]

A digital use of a push–pull configuration is the output of TTL and related families. The upper transistor is functioning as an active pull-up, in linear mode, while the lower transistor works digitally. For this reason they are not capable of supplyingsourcing as much current as they can ''sink'' (typically 20 times less). Because of the way these circuits are drawn schematically, with two transistors stacked vertically, normally with a level shifting diode in between, they are called "'''totem pole'''" outputs.

A disadvantage of simple push–pull outputs is that two or more of them cannot be connected together, because if one tried to pull while another tried to push, the transistors could be damaged. To avoid this restriction, some push–pull outputs have a third state in which both transistors are switched off. In this state, the output is said to be ''floating'' (or, to use a proprietary term, [[Three-state logic|''tri-stated'']]).