Content deleted Content added
sep lede, sort items |
257-bit wide integers, not a typo, "Integer — Signed 257-bit integers, representing integer numbers in the range −2^256 ...2^256 −1, as well as a special “not-a-number” value NaN." and "Cell — A TVM cell consists of at most 1023 bits of data, and of at most four references to other cells. All persistent data (including TVM code) in the TON Blockchain is represented as a collection of TVM cells" |
||
Line 1:
{{N-bit|256|(32 [[octet (computing)|octets]])}}
{{
There are currently no mainstream general-purpose [[CPU|processors]] built to operate on 256-bit integers or addresses, though a number of processors do operate on 256-bit data.
Line 12:
==Hardware==
[[File:Sharp PC-MM2 frontal view.jpg|thumb|Laptop computer using an [[Efficeon]] processor]]
CPUs feature [[SIMD]] instruction sets ([[Advanced Vector Extensions]] and the [[FMA instruction set]] etc.) where 256-bit vector [[processor register|register]]s are used to store several smaller numbers, such as eight 32-bit [[floating-point]] numbers, and a single [[CPU instruction|instruction]] can operate on all these values in parallel. However, these processors do not operate on individual numbers that are 256 binary digits in length, only their [[processor register|registers]] have the size of 256-bits. Binary digits are found together in [[128-bit computing|128-bit]] collections.
Modern [[GPU]] chips move data across a 256-bit memory bus (or possibly a [[512-bit computing|512-bit]] bus with [[High Bandwidth Memory|HBM3]]<ref>{{Cite web|last=April 2021|first=Scharon Harding 15|date=2021-04-15|title=What Are HBM, HBM2 and HBM2E? A Basic Definition|url=https://www.tomshardware.com/reviews/glossary-hbm-hbm2-high-bandwidth-memory-definition,5889.html|access-date=2021-09-11|website=Tom's Hardware|language=en}}</ref>).
The [[Transmeta Efficeon|Efficeon]] processor was [[Transmeta]]'s second-generation 256-bit [[VLIW]] design which employed a software engine to convert code written for [[x86]] processors to the native instruction set of the chip.<ref>{{Cite web|url=http://datasheets.chipdb.org/Transmeta/pdfs/brochures/efficeon_tm8300_processor.pdf|title=Transmeta Efficeon TM8300 Processor|publisher=[[Transmeta Corporation]]|archive-url=https://web.archive.org/web/20190210132436/http://datasheets.chipdb.org/Transmeta/pdfs/brochures/efficeon_tm8300_processor.pdf|archive-date=10 February 2019|url-status=live}}</ref><ref>{{Cite web|url=http://www.pcworld.com/article/101516/transmeta_unveils_plans_for_tm8000_processor.html|title=Transmeta Unveils Plans for TM8000 Processor|last=Williams|first=Martyn|date=29 May 2002|website=[[PC World]]|archive-url=https://web.archive.org/web/20100414160937/http://www.pcworld.com/article/101516/transmeta_unveils_plans_for_tm8000_processor.html|archive-date=14 April 2010|url-status=dead}}</ref>
Line 25:
* Researchers at the [[University of Cambridge]] use a 256-bit capability pointer, which includes capability and addressing information, on their CHERI capability system.<ref>{{cite web|url=http://www.csl.sri.com/users/neumann/2012resolve-cheri.pdf|title=CHERI: a research platform deconflating hardware virtualization and protection|last=Watson|first=Robert N. M.|author-link=Robert Watson (computer scientist)|last2=Neumann|first2=Peter G.|author2-link=Peter G. Neumann|date=3 March 2012|work=Unpublished workshop paper for RESoLVE’12, March 3, 2012, London, UK|publisher=[[SRI International]] Computer Science Laboratory|last3=Woodruff|first3=Jonathan|last4=Anderson|first4=Jonathan|last5=Anderson|first5=Ross|author-link5=Ross J. Anderson|last6=Dave|first6=Nirav|last7=Laurie|first7=Ben|author-link7=Ben Laurie|last8=Moore|first8=Simon W.|last9=Murdoch|first9=Steven J.|author-link9=Steven Murdoch|first10=Philip|last10=Paeps|first11=Michael|last11=Roe|first12=Hassen|last12=Saidi}}</ref>
* [[SHA-256]] hash function.
* [[Smart contract]]s use 256- or 257-bit integers; 256-bit words for the [[Ethereum Virtual Machine]]. "We realize that a 257 bits byte is quite unusual, but for smart contracts it is ok to have at least 256 bits numbers. The leading VM for smart contracts, Ethereum VM, introduced this practice and other blockchain VMs followed."<ref>{{Cite web|first=Dmitriy |last=Borisenkov |date=October 23, 2019|title=[llvm-dev] RFC: On non 8-bit bytes and the target for it|url=https://lists.llvm.org/pipermail/llvm-dev/2019-October/136115.html|access-date=2021-09-11}}</ref>
==See also==
| |||