Pulse transition detector: Difference between revisions

Revision as of 10:38, 6 August 2020

Revision as of 05:55, 23 September 2021

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The PTD consists of a delay gate (which delays the clock signal) and the clock signal itself passed through a [[NAND gate]] and then inverted.

The benefit of edge triggering is that it removes the problems of zeroes and ones catching associated with pulse triggered flipflops (e.g. [[Flip-flop_(electronics)#Master.E2.80.93slave_.28pulseMaster–slave edge-triggered.29_D_flip D flip-flop|master slave flip flops]]).

{{DEFAULTSORT:Pulse Transition Detector}}