Parallel SCSI: Difference between revisions

Revision as of 16:17, 20 July 2021

Revision as of 14:32, 23 September 2021

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===Ultra-3===

Ultra-3 includes five new optional features:

This standard includes five new optional features, which lead manufacturers to decide on two substandards to ensure consistent performance.{{elucidate|reason=How does 5 optional features lead to 2 substandards?|date=July 2021}} First introduced as '''Ultra-160''' toward the end of 1999, this iteration improved on the Ultra-2 standard by doubling the transfer rate to 160&nbsp;MB/s through the use of [[Double data rate|double-transition clocking]], and offered new features such as [[cyclic redundancy check|CRC]], a robust error-correcting process more suited for high-speed operation than the parity checking used previously, and ___domain validation for negotiating maximum performance for each device on the chain.<ref>{{cite journal|title=The Last Word on SCSI|last=Norris|first=Jim|journal=[[Maximum PC]]|date=March 2002|page=50|url=https://books.google.com/books?id=0gEAAAAAMBAJ&pg=PA50}}</ref> <!--[[User:Kvng/RTH]]-->

#Doubling the transfer rate to 160&nbsp;MB/s through the use of [[Double data rate|double-transition clocking]]

#[[cyclic redundancy check|CRC]], a robust error-correcting process more suited for high-speed operation than the parity checking used previously

#Domain validation for negotiating maximum performance for each device on the chain

#Packetization protocol with a reduced number of bus communication phases for less command and protocol overhead

#Quick arbitration and selection reduces arbitration time by eliminating bus free time

First introduced as '''Ultra-160''' toward the end of 1999, this iteration improved on the Ultra-2 standard adding the first three improvements.<ref>{{cite journal|title=The Last Word on SCSI|last=Norris|first=Jim|journal=[[Maximum PC]]|date=March 2002|page=50|url=https://books.google.com/books?id=0gEAAAAAMBAJ&pg=PA50}}</ref>

However, Ultra-160 merely represents a subset of Ultra-3, lacking its two other new features, packetization and quick arbitration and selection (QAS). Packetization refers to a protocol with a reduced number of bus communication phases for less command and protocol overhead, while QAS reduces arbitration time by eliminating bus free time. Devices supporting these features were marketed as '''Ultra-160+''' or U3. 8-bit bus width as well as HVD operation were eliminated starting with Ultra-3.<ref name="MuellerSoper2006">{{cite book|author1=Scott Mueller|author2=Mark Edward Soper|author3=Barrie Sosinsky|title=Upgrading and Repairing Servers|url=https://books.google.com/books?id=9cLFf_1PBnkC&pg=PT724|date=24 April 2006|publisher=Pearson Education|isbn=978-0-13-279698-9}}</ref>

However, Ultra-160 merely represents a subset of Ultra-3, lacking its two other new features, packetization and quick arbitration and selection (QAS). Packetization refers to a protocol with a reduced number of bus communication phases for less command and protocol overhead, while QAS reduces arbitration time by eliminating bus free time. Devices supporting theseall five features were marketed as '''Ultra-160+''' or Ultra-3 (U3). 8-bit bus width as well as HVD operation were eliminated starting with Ultra-3.<ref name="MuellerSoper2006">{{cite book|author1=Scott Mueller|author2=Mark Edward Soper|author3=Barrie Sosinsky|title=Upgrading and Repairing Servers|url=https://books.google.com/books?id=9cLFf_1PBnkC&pg=PT724|date=24 April 2006|publisher=Pearson Education|isbn=978-0-13-279698-9}}</ref><!--[[User:Kvng/RTH]]-->

===Ultra-320===