Intel 5-level paging: Difference between revisions

Revision as of 00:56, 7 September 2021

Revision as of 08:49, 28 September 2021

Line 19:

== Drawbacks ==

Adding another level of indirection makes [[page table]] "walks" longer.<ref>{{Cite book|title=MICRO-50 : the 50th Annual IEEE/ACM International Symposium on Microarchitecture : proceedings : October 14-18, 2017, Cambridge, MA|others=Institute of Electrical and Electronics Engineers., IEEE Computer Society., ACM Special Interest Group on Microprogramming|isbn=9781450349529|___location=New York, New York|oclc=1032337814|date = 14 October 2017}}</ref> A page table walk occurs when either the processor's [[memory management unit]] or the memory management code in the operating system navigates the tree of page tables to find the [[page table entry]] corresponding to a virtual address.<ref>{{Cite web|url=http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0301h/I1026235.html|title=ARM Information Center|website=infocenter.arm.com|access-date=2018-04-26}}</ref><ref name="x86-software-developers-manual">{{Cite book|url=https://software.intel.com/sites/default/files/managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf|title=Intel® 64 and IA-32 Architectures Software Developer's Manual|publisher=[[Intel Corporation]]|year=2018}}</ref>{{Rp|2806}} This means that, in the worst case, the processor or the memory manager has to access physical memory six times for a single virtual memory access, rather than five for the previous iteration of x86-64 processors. This results in slightly reduced memory access speed.<ref name="cse-451-paging-tlbs-slides" /> In practice this cost is greatly mitigated by caches such as the [[translation lookaside buffer]] (TLB).<ref name="cse-451-paging-tlbs-slides">{{Cite web|url=https://courses.cs.washington.edu/courses/cse451/08au/lectures/10-paging_TLBs.pdf|title=CSE 451: Operating Systems: Paging & TLBs|last=Levy|first=Hank|author-link=Hank Levy (computer scientist)|date=Autumn 2008|website=[[University of Washington]]|access-date={{date|2018-04-26}} April 2018}}</ref> Further extensions may reduce page walks by using 4096 128-bit page table entries, and allow a larger 64&nbsp;KB page allocation size and backward compatibility with 4&nbsp;KB page operations. <Ref name=VA64>{{cite patent | country = US | number = 9858198 | status = patent | title = 64KB page system that supports 4KB page operation | pridate = 2015-06-26 | fdate = 2015-06-26 | pubdate = 2016-12-29 | gdate = 2018-01-02 | invent1 = Larry Seiler | assign1 = Intel Corp.}} </ref>

== References ==