PICs typically have a common set of registers: Interruptinterrupt Requestrequest Registerregister (IRR), Inin-Serviceservice Registerregister (ISR), Interruptand Maskinterrupt Registermask register (IMR). The IRR specifies which interrupts are pending acknowledgement, and is typically a symbolic register which can not be directly accessed. The ISR register specifies which interrupts have been acknowledged, but are still waiting for an [[Endend of interrupt|End Of Interrupt]] (EOI). The IMR specifies which interrupts are to be ignored and not acknowledged. A simple register schema such as this allows up to two distinct interrupt requests to be outstanding at one time, one waiting for acknowledgement, and one waiting for EOI.
There are a number of common priority schemas in PICs including hard priorities, specific priorities, and rotating priorities.
