Digital signal processor: Difference between revisions

Revision as of 19:10, 21 January 2022

Revision as of 16:15, 28 January 2022

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***[[Fast Fourier transform]] (FFT)

*related instructions:

**[[Single instruction, multiple data|SIMD]]

**[[VLIW]]

*Specialized instructions for [[modular arithmetic|modulo]] addressing in [[circular buffer|ring buffers]] and bit-reversed addressing mode for [[Fast Fourier transform|FFT]] cross-referencing

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[[CEVA, Inc.]] produces and licenses three distinct families of DSPs. Perhaps the best known and most widely deployed is the CEVA-TeakLite DSP family, a classic memory-based architecture, with 16-bit or 32-bit word-widths and single or dual [[Multiply–accumulate operation|MACs]]. The CEVA-X DSP family offers a combination of VLIW and SIMD architectures, with different members of the family offering dual or quad 16-bit MACs. The CEVA-XC DSP family targets [[Software-defined radio|Software-defined Radio (SDR)]] modem designs and leverages a unique combination of VLIW and Vector architectures with 32 16-bit MACs.

[[Analog Devices]] produce the [[Super Harvard Architecture Single-Chip Computer|SHARC]]-based DSP and range in performance from 66 MHz/198 [[MFLOPS]] (million floating-point operations per second) to 400 MHz/2400 MFLOPS. Some models support multiple [[binary multiplier|multiplier]]s and [[Arithmetic logic unit|ALU]]s, [[Single instruction, multiple data|SIMD]] instructions and audio processing-specific components and peripherals. The [[Blackfin]] family of embedded digital signal processors combine the features of a DSP with those of a general use processor. As a result, these processors can run simple [[operating system]]s like [[μCLinux]], velocity and [[Nucleus RTOS]] while operating on real-time data.

[[NXP Semiconductors]] produce DSPs based on [[TriMedia (mediaprocessor)|TriMedia]] [[VLIW]] technology, optimized for audio and video processing. In some products the DSP core is hidden as a fixed-function block into a [[System-on-a-chip|SoC]], but NXP also provides a range of flexible single core media processors. The TriMedia media processors support both [[fixed-point arithmetic]] as well as [[floating-point arithmetic]], and have specific instructions to deal with complex filters and entropy coding.