Latency oriented processor architecture: Difference between revisions

Revision as of 22:36, 29 June 2021

Revision as of 16:21, 28 January 2022

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==Flynn's taxonomy==

{{Main|Flynn's taxonomy}}

Latency oriented processor architectures would normally fall into the category of [[Single instruction, single data|SISD]] classification under flynn's taxonomy. This implies a typical characteristic of latency oriented processor architectures is to execute a single task operating on a single data stream. Some [[Single instruction, multiple data|SIMD]] style multimedia extensions of popular instruction sets, such as Intel [[MMX (instruction set)|MMX]] and [[Streaming SIMD Extensions|SSE]] instructions, should also fall under the category of latency oriented processor architectures;<ref name=YanSohilin2016/> because, although they operate on a large data set, their primary goal is also to reduce overall latency for the entire task at hand.

==Implementation techniques==