Advanced Programmable Interrupt Controller: Difference between revisions

Revision as of 03:33, 24 January 2022

Revision as of 10:57, 19 February 2022

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==I/O APICs==

I/O APICs contain a redirection table, which is used to route the interrupts it receives from peripheral buses to one or more local APICs. Early I/O APICs (like 82489DX, SIO.A and PCEB/ESC) only had support for 16 interrupt lines, but later ones like 82093AA (separate chip for PIIX3/PIIX4) had support for 24 interrupt lines.<ref name="msi">James Coleman, [http://www.intel.com/content/dam/www/public/us/en/documents/white-papers/msg-signaled-interrupts-paper.pdf Reducing Interrupt Latency Through the Use of Message Signaled Interrupts], pp. 10-11</ref> It was packaged as a 64-Pin [[PQFP]].<ref name="i82093AA">{{cite web|url=http://www.intel.com/design/chipsets/datashts/290566.htm|title=Resource & Design Center for Development with Intel|website=Intel}}</ref> The 82093AA normally connected to the [[PIIX3]]/[[PIIX4]] and used its integrated legacy 8259 PICs.<ref name="i82093AA"/> The [[I/O Controller Hub#ICH|ICH1]] reintegratedand an[[Intel I/O815]] APIC, likeintegrated the PIIX predecessor SIO.A (for ISA) and PCEBI/ESCO (for EISA)APIC.

According to a 2009 Intel benchmark using [[Linux]], the I/O APIC reduced interrupt latency by a factor of almost three relative to the 8259 emulation (XT-PIC), while using MSI reduced the latency even more, by a factor of nearly seven relative to the XT-PIC baseline.<ref>James Coleman, [http://www.intel.com/content/dam/www/public/us/en/documents/white-papers/msg-signaled-interrupts-paper.pdf Reducing Interrupt Latency Through the Use of Message Signaled Interrupts], p. 19</ref>