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[[File:MIPS Architecture (Pipelined).svg|thumb|right|300px|[[Instruction pipelining|Pipelined]] MIPS, showing the five stages: instruction fetch, instruction decode, execute, memory access and write back.]]
The first MIPS microprocessor, the ''[[R2000 (microprocessor)|R2000]]'', was announced in 1985. It added multiple-cycle multiply and divide instructions in a somewhat independent on-chip unit. New instructions were added to retrieve the results from this unit back to the [[processor register]] file; these result-retrieving instructions were [[interlock|interlocked]].
The R2000 could be booted either [[Endianness|''big-endian'' or ''little-endian'']]. It had thirty-one 32-bit general purpose registers, but no [[status register]] (''condition code register'' (CCR), the designers considered it a potential bottleneck), a feature it shares with the [[AMD 29000]], the [[DEC Alpha]], and [[RISC-V]]. Unlike other registers, the [[program counter]] is not directly accessible.
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