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CodingKoopa (talk | contribs) Specify that MIPS is a family of ISAs, rather than a specific ISA itself. MIPS is a family in the same way x86 is. |
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'''MIPS''' ('''Microprocessor without Interlocked Pipelined Stages''')<ref>{{Cite book|title=Computer Organization and Design|last=Patterson|first=David|publisher=Elsevier|year=2014|isbn=978-0-12-407726-3|url=http://booksite.elsevier.com/9780124077263/downloads/historial%20perspectives/section_4.16.pdf|pages=4.16–4|access-date=November 28, 2018|archive-date=September 4, 2019|archive-url=https://web.archive.org/web/20190904223729/https://booksite.elsevier.com/9780124077263/downloads/historial%20perspectives/section_4.16.pdf|url-status=live}}</ref> is a family of [[reduced instruction set computer]] (RISC) [[instruction set architecture]]s (ISA)<ref name=Price1995>Price, Charles (September 1995). ''MIPS IV Instruction Set'' (Revision 3.2), MIPS Technologies, Inc.</ref>{{rp|A-1}}<ref name=Sweetman1999>{{cite book|last=Sweetman|first=Dominic|date=1999|title=See MIPS Run|publisher=Morgan Kaufmann Publishers, Inc.|isbn=1-55860-410-3}}</ref>{{rp|19}} developed by MIPS Computer Systems, now [[MIPS Technologies]], based in the United States.
There are multiple versions of MIPS: including MIPS I, II, III, IV, and V; as well as five releases of MIPS32/64 (for 32- and 64-bit implementations, respectively). The early MIPS architectures were 32-bit; 64-bit versions were developed later. As of April 2017, the current version of MIPS is MIPS32/64 Release 6.<ref>{{cite web|url= https://www.mips.com/products/architectures/mips32-3/|title= MIPS32 Architecture|website= MIPS|access-date= March 20, 2020|archive-date= March 21, 2020|archive-url= https://web.archive.org/web/20200321031349/https://www.mips.com/products/architectures/mips32-3/|url-status= live}}</ref><ref>{{cite web|url= https://www.mips.com/products/architectures/mips64/|title= MIPS64 Architecture|website= MIPS|access-date= March 20, 2020|archive-date= February 2, 2020|archive-url= https://web.archive.org/web/20200202235833/https://www.mips.com/products/architectures/mips64/|url-status= live}}</ref> MIPS32/64 primarily differs from MIPS I–V by defining the privileged kernel mode System Control Coprocessor in addition to the user mode architecture.
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