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The dynamic power (''[[switching power]]'') dissipated by a chip is ''C·V<sup>2</sup>·A·f'', where C is the [[capacitance]] being switched per clock cycle, V is [[voltage]], A is the Activity Factor<ref name="ActivityFactor">{{cite journal | title = Timing-aware power-optimal ordering of signals | author = K. Moiseev, A. Kolodny and S. Wimer | journal = ACM Transactions on Design Automation of Electronic Systems |volume=13 |issue=4 |date=September 2008| pages = 1–17 | doi = 10.1145/1391962.1391973 | s2cid = 18895687 }}</ref> indicating the average number of switching events per clock cycle by the transistors in the chip (as a unitless quantity) and f is the clock frequency.<ref>{{Cite book|first=J. M.|last= Rabaey|title= Digital Integrated Circuits|publisher= Prentice Hall|year= 1996}}</ref>
Voltage is therefore the main determinant of power usage and heating.<ref>{{cite web|url=https://software.intel.com/en-us/blogs/2014/02/19/why-has-cpu-frequency-ceased-to-grow|author= Victoria Zhislina|date=2014-02-19|title=Why has CPU frequency ceased to grow?|publisher=Intel}}</ref> The voltage required for stable operation is determined by the frequency at which the circuit is clocked, and can be reduced if the frequency is also reduced.<ref>https://www.usenix.org/legacy/events/hotpower/tech/full_papers/LeSueur.pdf {{Bare URL PDF|date=March 2022}}</ref> Dynamic power alone does not account for the total power of the chip, however, as there is also static power, which is primarily because of various leakage currents. Due to static power consumption and asymptotic execution time it has been shown that the energy consumption of software shows convex energy behavior, i.e., there exists an optimal CPU frequency at which energy consumption is minimized.<ref>{{cite arXiv | title = The Energy/Frequency Convexity Rule: Modeling and Experimental Validation on Mobile Devices |year=2014 | eprint = 1401.4655|author1=Karel De Vogeleer |last2=Memmi |first2=Gerard |last3=Jouvelot |first3=Pierre |last4=Coelho |first4=Fabien |class=cs.OH }}</ref>
[[Subthreshold leakage|Leakage current]] has become more and more important as transistor sizes have become smaller and threshold voltage levels are reduced. A decade ago, dynamic power accounted for approximately two-thirds of the total chip power. The power loss due to leakage currents in contemporary CPUs and SoCs tend to dominate the total power consumption. In the attempt to control the leakage power, [[High-κ dielectric|high-k metal-gates]] and power gating have been common methods.
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=== Intel ===
[[Intel]]'s CPU throttling technology, [[SpeedStep]], is used in its mobile and desktop CPU lines.
=== AMD ===
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