FPGA prototyping: Difference between revisions

Revision as of 12:10, 5 December 2021

Revision as of 07:03, 14 March 2022

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{{Use American English|date = March 2019}}

{{Short description|Prototyping integrated circuit designs on FPGA}}

{{Further|Field-programmable gate array}}

{{Use American English|date = March 2019}}

{{Use mdy dates|date = March 2019}}

{{Further|Field-programmable gate array}}{{multiple issues|

{{original research|date=September 2012}}

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===Balance FPGA resources while creating design partitions===

When creating circuit partitions, engineers should first observe the available resources the FPGA offers, since the design will be placed onto the FPGA fabric.<ref name="Aldec" /> The architecture of each FPGA is dependent on the manufacturer, but the main goal in design partitioning is to have an even balance of FPGA resource utilization. Various FPGA resources include [[Lookuplookup table|lookup tables]]s (LUTs), [[D flip-flops]], block [[Random-access memory|RAMs]], [[Digitaldigital signal processor|digital signal processors]]s (DSPs), clock buffers, etc. Prior to balancing the design partitions, it is also valuable to the user to perform global [[logic optimization]] to remove any redundant or unused logic. A typical problem that arises with creating balanced partitions is that it may lead to timing or resource conflict if the cut is on many signal lines. To have a fully optimized partitioning strategy, the engineer must consider issues such as timing/power constraints and placement and routing while still maintaining a balanced partition amongst the FPGAs. Strictly focusing on a single issue during a partition may create several issues in another.

===Placing and routing partitions===

In order to achieve optimal place and routing for partitioned designs, the engineer must focus on FPGA pin count and inter-FPGA signals. After partitioning the design into separate FPGAs, the number of inter-FPGA signals must not to exceed the pin count on the FPGA.<ref>http://www.fpga-faq.com/FAQ_Pages/prototyping.pdf {{Bare URL PDF|date=March 2022}}</ref> This is very difficult to avoid when circuit designs are immense, thus signals must utilize strategies such as [[time-division multiplexing]] (TDM) which multiple signals can be transferred over a single line.<ref>{{Cite web|url=http://www.inetdaemon.com/tutorials/telecom/t-carrier/time-division_multiplexing.shtml|title=Time-Division Multiplexing|website=www.inetdaemon.com|language=en-US|access-date=2018-10-08}}</ref> These multiple signals, called sub-channels, take turns being transferred over the line over a time slot. When the TDM ratio is high, the bus clock frequency has to be reduced to accommodate time slots for each sub-channel. By reducing the clock frequency the throughput of the system is hindered.<ref name=Aldec/>

===Timing requirements===