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Made the description of the priority encoder output easier to understand. Tags: Mobile edit Mobile web edit |
/* Recursive construction of priority encoders Tweak cites, consol |
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The depth of the proposed structure is <math>\lceil\log_kn\rceil</math>, while the hardware area complexity is <math>\mathcal{O}(n)</math>. If Altera’s Stratix V or equivalent device is used, <math>k=4</math> is recommended to achieve higher performance and area compression, since the mux can be implemented using 6-LUT, hence an entire ALM.
An open-source Verilog generator for the recursive priority-encoder is available online.<ref name=II2DCAM>{{Cite web|url=https://github.com/AmeerAbdelhadi/Indirectly-Indexed-2D-Binary-Content-Addressable-Memory-BCAM/blob/master/pe |
{{cite book |first=A.M.S. |last=Abdelhadi |first2=G.G.F. |last2=Lemieux |chapter=Modular SRAM-Based Binary Content-Addressable Memories |chapter-url=http://www.ece.ubc.ca/~lemieux/publications/abdelhadi-fccm2015.pdf |title=2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines |publisher=IEEE |___location= |date=2015 |isbn=978-1-4799-9969-9 |pages=207–214 |doi=10.1109/FCCM.2015.69}}</ref>
[[File:PE-recursion.svg|alt=Priority-encoder (left) symbol (right) recursive definition.|center|thumb|416x416px|Priority-encoder (left) symbol (right) recursive definition.]]
A behavioral description of priority encoder in Verilog is as follows.<ref
// behavioural description of priority enconder;
// https://github.com/AmeerAbdelhadi/Indirectly-Indexed-2D-Binary-Content-Addressable-Memory-BCAM
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