Advanced Programmable Interrupt Controller: Difference between revisions

Revision as of 10:57, 19 February 2022

Revision as of 08:01, 25 March 2022

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==Discrete APIC==

The first-generation Intel APIC chip, the 82489DX, which was meant to be used with [[Intel 80486]] and early Pentium processors, is actually an external local and I/O APIC in one circuit. The Intel MP 1.4 specification refers to it as "discrete APIC" in contrast with the "integrated APIC" found in most of the Pentium processors.<ref>[http://www.intel.com/design/archives/processors/pro/docs/242016.htm Intel MultiProcessor Specification], version 1.4, page 1-4, May 1997</ref> The 82489DX had 16 interrupt lines;<ref name="Ram2001">{{cite book|author=Badri Ram|title=Adv Microprocessors Interfacing|url=https://books.google.com/books?id=eVcEWDIeTYcC&pg=PT314|year=2001|publisher=Tata McGraw-Hill Education|isbn=978-0-07-043448-6|page=314}}</ref> it also had a quirk that it could lose some ISA interrupts.<Refref>http://people.freebsd.org/~fsmp/SMP/papers/apicsubsystem.txt {{Bare URL plain text|date=March 2022}}</ref>

In a multiprocessor 486 system, each CPU had to be paired with its own 82489DX; additionally a supplementary 82489DX had to be used as I/O APIC. The 82489DX could not emulate the 8259A (XT-PIC) so these also had to be included as physical chips for backwards compatibility.<ref>Intel MultiProcessor Specification, version 1.4, page 5-3, May 1997</ref> The 82489DX was a packaged as a 132-pin [[PQFP]].<ref name="Ram2001"/>

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Local APICs (LAPICs) manage all external interrupts for some specific processor in an SMP system. In addition, they are able to accept and generate [[inter-processor interrupt]]s (IPIs) between LAPICs. LAPICs may support up to 224 usable [[interrupt]] vectors from an I/O APIC. Vector numbers 0 to 31, out of 0 to 255, are reserved for exception handling by x86 processors.

All Intel processors starting with the P5 microarchitecture ([[P54C]]) have a built-in local APIC.<ref name="Mueller2011">{{cite book|author=Scott M. Mueller|title=Upgrading and Repairing PCs|year=2011|publisher=Que Publishing|isbn=978-0-13-268218-3|page=242|edition=20th}}</ref><ref name="timer" /> However, if the local APIC is disabled in a P5 processor, it cannot be re-enabled by software; this limitation no longer exists in the [[P6 (microarchitecture)|P6 processors]] and later ones.<ref name="timer" />

The [[Message Signaled Interrupts]] (MSI) feature of the PCI 2.2 and later specifications cannot be used without the local APIC being enabled.<ref name="up">{{cite web|url=http://msdn.microsoft.com/en-us/windows/hardware/gg462964.aspx|title=Windows Hardware Dev Center|website=msdn.microsoft.com}}</ref> Use of MSI obviates the need for an I/O APIC. Additionally, up to 224 interrupts are supported in MSI mode, and IRQ sharing is not allowed.<ref name="msi"/>

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Another advantage of the local APIC is that it also provides a high-resolution (on the order of one [[microsecond]] or better) timer that can be used in both interval and one-off mode.<ref name="timer">Uwe Walter, Vincent Oberle [http://telematics.tm.kit.edu/publications/Files/61/walter_ibm_linux_challenge.pdf μ-second precision timer support for the Linux kernel]</ref>

The APIC timer had its initial acceptance woes. A Microsoft document from 2002 (which advocated for the adoption of [[High Precision Event Timer]] instead) criticized the LAPIC timer for having "poor resolution" and stating that "the clocks silicon is sometimes very buggy".<Refref>[http://msdn.microsoft.com/en-us/library/windows/hardware/gg463347.aspx Guidelines For Providing Multimedia Timer Support], September 20, 2002</ref> Nevertheless, the APIC timer is used for example by [[Windows 7]] when [[Profiling (computer programming)|profiling]] is enabled, and by [[Windows 8]] in all circumstances. (Before Windows 8 claimed exclusive rights to this timer, it was also used by some programs like [[CPU-Z]].) Under Microsoft Windows the APIC timer is not a shareable resource.<ref>[http://social.msdn.microsoft.com/Forums/windowsdesktop/en-US/5d075378-a45f-433b-a3f7-73f974ec962f/windows-8-and-apic-timer?forum=wdk Windows 8 and APIC timer] {{webarchive |url=https://web.archive.org/web/20140222070735/http://social.msdn.microsoft.com/Forums/windowsdesktop/en-US/5d075378-a45f-433b-a3f7-73f974ec962f/windows-8-and-apic-timer?forum=wdk |date=February 22, 2014 }}</ref>

The aperiodic interrupts offered by the APIC timer are used by the [[Linux kernel]] [[tickless kernel]]

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== Issues ==

{{unreferenced| section|date=February 2014}}

There are a number of known bugs in implementations of APIC systems, especially with concern to how the [[Intel 8254|8254]] is connected. Defective [[BIOS]]es may not set up interrupt routing properly, or provide incorrect [[Advanced Configuration and Power Interface|ACPI]] tables and Intel [[MultiProcessor Specification]] (MPS) tables.

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* More information on the Intel x2APIC Architecture can be found in the ''Intel 64 and IA-32 [http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html Architectures Software Developer's Manuals]

{{Intel}}

[[Category:Motherboard]]

[[Category:Interrupts]]